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motorola mc68307 user? manual v preface the mc68307 user? manual describes the programming, capabilities, and operation of the mc68307 and the mc68000 family programmer? reference manual provides instruction details for the mc68307. the organization of this manual is as follows: section 1 introduction section 2 signal description section 3 bus operation section 4 ec000 core processor section 5 system integration module section 6 dual timer module section 7 m-bus interface module section 8 serial module section 9 ieee 1149.1 test access port section 10 applications information section 11 electrical characteristics section 12 ordering information and mechanical data
motorola mc68307 user? manual vii table of contents section 1 introduction 1.1 m68300 family ............................................................................................. 1-3 1.1.1 organization ............................................................................................... 1-3 1.1.2 advantages................................................................................................. 1-3 1.2 mc68307 architecture .................................................................................. 1-4 1.2.1 ec000 core processor............................................................................... 1-4 1.2.2 system integration module (sim07) ........................................................... 1-4 1.2.2.1 external bus interface .............................................................................. 1-5 1.2.2.2 chip select and wait state generation ................................................... 1-5 1.2.2.3 system configuration and protection ....................................................... 1-5 1.2.2.4 parallel input/output ports ....................................................................... 1-5 1.2.2.5 interrupt controller.................................................................................... 1-6 1.2.3 timer module.............................................................................................. 1-6 1.2.4 uart module ............................................................................................. 1-6 1.2.5 m-bus module............................................................................................. 1-6 1.2.6 test access port......................................................................................... 1-7 section 2 signal description 2.1 bus signals ................................................................................................... 2-5 2.1.1 address bus (a23?0) ............................................................................... 2-5 2.1.1.1 address bus (a23?8) ............................................................................. 2-5 2.1.1.2 address bus (ad7?d0) .......................................................................... 2-5 2.1.2 data bus (d15?0) .................................................................................... 2-6 2.2 chip selects.................................................................................................. 2-6 2.2.1 chip select 0 (cs0 ) .................................................................................... 2-6 2.2.2 chip select 1 (cs1 ) .................................................................................... 2-6 2.2.3 chip select 2 (cs2 , cs2b , cs2c , cs2d ) ................................................. 2-6 2.2.4 chip select 3 (cs3 ) .................................................................................... 2-7 2.3 bus control signals ...................................................................................... 2-7 2.3.1 data transfer acknowledge (dtack )........................................................ 2-7 2.3.2 address strobe (as )................................................................................... 2-8 2.3.3 read/write (r/w ) ....................................................................................... 2-8 2.3.4 data strobes, upper and lower (uds , lds ) ............................................. 2-8 2.3.5 8051 address latch enable (ale) ............................................................. 2-9 2.3.6 8051-compatible bus read (rd ) ............................................................... 2-9 2.3.7 8051-compatible bus write (wr ) .............................................................. 2-9 2.3.8 bus width select for cs0 (busw0) ........................................................... 2-9 2.4 exception control signals............................................................................. 2-9 thi d t t d ith f m k 4 0 4
table of contents viii mc68307 user? manual motorola 2.4.1 reset (reset )........................................................................................... 2-9 2.4.2 power-on reset (rstin ) ......................................................................... 2-10 2.4.3 halt (halt )............................................................................................... 2-10 2.4.4 bus request (br /pa5)............................................................................. 2-10 2.4.5 bus grant (bg /pa6) ................................................................................. 2-10 2.4.6 bus grant acknowledge (bgack /pa7) .................................................. 2-10 2.5 clock signals .............................................................................................. 2-10 2.5.1 crystal oscillator (extal, xtal)............................................................. 2-10 2.5.2 clock output (clkout)........................................................................... 2-11 2.6 test signals ................................................................................................ 2-11 2.6.1 test clock (tck) ...................................................................................... 2-11 2.6.2 test mode select (tms)........................................................................... 2-11 2.6.3 test data in (tdi)..................................................................................... 2-11 2.6.4 test data out (tdo) ................................................................................ 2-11 2.7 m-bus i/o signals....................................................................................... 2-11 2.7.1 serial clock (scl/pb0) ............................................................................ 2-11 2.7.2 serial data (sda/pb1) ............................................................................. 2-12 2.8 uart i/o signals ....................................................................................... 2-12 2.8.1 transmit data (txd/pb2) ......................................................................... 2-12 2.8.2 receive data (rxd/pb3).......................................................................... 2-12 2.8.3 request-to-send (rts /pb4)................................................................... 2-12 2.8.4 clear-to-send (cts /pb5)........................................................................ 2-12 2.9 timer i/o signals ........................................................................................ 2-12 2.9.1 timer 1 input (tin1/pb6) ......................................................................... 2-12 2.9.2 timer 2 input (tin2/pb7) ......................................................................... 2-13 2.9.3 timer 1 output (tout1 /pa3)................................................................... 2-13 2.9.4 timer 2 output (tout2 /pa4)................................................................... 2-13 2.10 interrupt request inputs ............................................................................. 2-13 2.10.1 interrupt inputs (int1 ?nt8 /pb8?b15).................................................. 2-13 2.10.2 non-maskable interrupt input (irq7 ) ....................................................... 2-13 2.11 use of pullup resistors .............................................................................. 2-13 2.12 signal index ................................................................................................ 2-14 section 3 bus operation 3.1 data transfer operations ............................................................................. 3-1 3.1.1 16-bit m68000 bus operation .................................................................... 3-1 3.1.2 16-bit m68000 bus read cycle ................................................................. 3-2 3.1.3 16-bit m68000 bus write cycle.................................................................. 3-5 3.1.4 read-modify-write cycle............................................................................ 3-8 3.1.5 cpu space cycle..................................................................................... 3-11 3.1.6 8-bit m68000 dynamically-sized bus ...................................................... 3-11 3.1.7 8051-bus operation ................................................................................. 3-13 3.2 bus arbitration ............................................................................................ 3-15 3.2.1 requesting the bus .................................................................................. 3-17
table of contents motorola mc68307 user? manual ix 3.2.2 receiving the bus grant........................................................................... 3-18 3.2.3 acknowledgment of mastership (three-wire bus arbitration only) ......... 3-18 3.3 bus arbitration control................................................................................ 3-19 3.4 bus error and halt operation ..................................................................... 3-27 3.4.1 bus error operation .................................................................................. 3-27 3.4.2 retrying the bus cycle ............................................................................. 3-29 3.4.3 halt operation........................................................................................... 3-30 3.4.4 double bus fault ...................................................................................... 3-31 3.5 reset operation.......................................................................................... 3-31 3.6 asynchronous operation ............................................................................ 3-32 3.7 synchronous operation .............................................................................. 3-35 section 4 ec000 core processor 4.1 features........................................................................................................ 4-1 4.2 processing states ......................................................................................... 4-1 4.3 programming model...................................................................................... 4-2 4.3.1 data format summary ............................................................................... 4-3 4.3.2 addressing capabilities summary .............................................................. 4-3 4.3.3 notation conventions ................................................................................. 4-4 4.4 ec000 core instruction set overview .......................................................... 4-6 4.5 exception processing ................................................................................... 4-9 4.5.1 exception vectors..................................................................................... 4-12 4.6 processing of specific exceptions .............................................................. 4-12 4.6.1 reset exception........................................................................................ 4-14 4.6.2 interrupt exceptions.................................................................................. 4-14 4.6.3 uninitialized interrupt exception ............................................................... 4-15 4.6.4 spurious interrupt exception .................................................................... 4-15 4.6.5 instruction traps ....................................................................................... 4-16 4.6.6 illegal and unimplemented instructions.................................................... 4-16 4.6.7 privilege violations ................................................................................... 4-17 4.6.8 tracing...................................................................................................... 4-17 4.6.9 bus error................................................................................................... 4-18 4.6.10 address error............................................................................................ 4-18 4.6.11 multiple exceptions................................................................................... 4-19 section 5 system integration module 5.1 module operation ......................................................................................... 5-2 5.1.1 mc68307 system configuration................................................................. 5-2 5.1.1.1 module base address register operation ............................................... 5-2 5.1.1.2 system control register functions .......................................................... 5-4 5.1.1.3 system protection functions .................................................................... 5-5 5.1.2 chip select and wait-state logic ............................................................... 5-5 5.1.2.1 programmable data-bus size .................................................................. 5-6
table of contents x mc68307 user? manual motorola 5.1.2.2 peripheral chip selects ............................................................................ 5-7 5.1.2.3 8051-compatible bus chip select ........................................................... 5-8 5.1.2.4 global chip select operation (reset defaults) ........................................ 5-8 5.1.2.5 overlap in chip select ranges ................................................................ 5-8 5.1.3 external bus interface logic....................................................................... 5-9 5.1.3.1 m68000 bus interface .............................................................................. 5-9 5.1.3.2 8051-compatible bus interface .............................................................. 5-10 5.1.3.3 port a, port b general-purpose i/o ports .............................................. 5-10 5.1.4 interrupt processing ................................................................................. 5-13 5.1.4.1 interrupt controller logic ........................................................................ 5-14 5.1.4.2 interrupt vector generation .................................................................... 5-15 5.1.4.3 irq7 non-maskable interrupt ................................................................ 5-17 5.1.4.4 general-purpose interrupt inputs ........................................................... 5-17 5.1.4.5 peripheral interrupt handling ................................................................. 5-18 5.1.5 low-power sleep logic............................................................................ 5-19 5.2 programming model ................................................................................... 5-20 5.2.1 system configuration and protection registers....................................... 5-22 5.2.1.1 module base address register (mbar) ................................................ 5-22 5.2.1.2 system control register (scr).............................................................. 5-23 5.2.1.3 system status register bits description ................................................ 5-23 5.2.1.4 system control register bits description. ............................................. 5-25 5.2.2 chip select registers ............................................................................... 5-30 5.2.2.1 base registers (br3?r0).................................................................... 5-30 5.2.2.2 option registers (or3?r0) ................................................................ 5-32 5.2.3 external bus interface control registers ................................................. 5-34 5.2.3.1 port a control register (pacnt) ........................................................... 5-34 5.2.3.2 port a data direction register (paddr) ............................................... 5-35 5.2.3.3 port a data register (padat) ............................................................... 5-35 5.2.3.4 port b control register (pbcnt) ........................................................... 5-36 5.2.3.5 port b data direction register (pbddr) ............................................... 5-36 5.2.3.6 port b data register (pbdat) ............................................................... 5-37 5.2.4 interrupt control registers ....................................................................... 5-38 5.2.4.1 latched interrupt control registers 1,2 (licr1,licr2)......................... 5-38 5.2.4.2 peripheral interrupt control register (picr).......................................... 5-39 5.2.4.3 programmable interrupt vector register (pivr) .................................... 5-40 5.3 mc68307 initialization procedure............................................................... 5-41 5.3.1 startup?old reset................................................................................. 5-41 5.3.2 sim configuration..................................................................................... 5-41 section 6 dual timer module 6.1 overview....................................................................................................... 6-1 6.2 module operation ......................................................................................... 6-1 6.2.1 general-purpose timer units..................................................................... 6-1 6.2.2 software watchdog timer .......................................................................... 6-3
table of contents motorola mc68307 user? manual xi 6.3 programming model...................................................................................... 6-4 6.3.1 general purpose timer units ..................................................................... 6-4 6.3.1.1 timer mode register (tmr1, tmr2) ....................................................... 6-4 6.3.1.2 timer reference registers (trr1, trr2)............................................... 6-5 6.3.1.3 timer capture registers (tcr1, tcr2) .................................................. 6-5 6.3.1.4 timer counter (tcn1, tcn2)................................................................... 6-5 6.3.1.5 timer event registers (ter1, ter2) ...................................................... 6-6 6.3.2 software watchdog timer .......................................................................... 6-7 6.3.2.1 watchdog reference register (wrr)...................................................... 6-7 6.3.2.2 watchdog counter register (wcr) ......................................................... 6-7 6.4 timer programming examples ..................................................................... 6-8 6.4.1 initialization and reference compare function.......................................... 6-8 6.4.2 event counting function and interrupts ..................................................... 6-9 6.4.3 input capture function ............................................................................... 6-9 6.4.4 watchdog usage example ....................................................................... 6-10 section 7 m-bus interface module 7.1 m-bus system configuration ........................................................................ 7-2 7.2 m-bus protocol ............................................................................................. 7-2 7.2.1 start signal ............................................................................................. 7-3 7.2.2 slave address transmission ...................................................................... 7-3 7.2.3 data transfer .............................................................................................. 7-3 7.2.4 repeated start signal ............................................................................ 7-4 7.2.5 stop signal ............................................................................................... 7-4 7.2.6 arbitration procedure.................................................................................. 7-4 7.2.7 clock synchronization ................................................................................ 7-4 7.2.8 handshaking............................................................................................... 7-5 7.2.9 clock stretching.......................................................................................... 7-5 7.3 programming model...................................................................................... 7-5 7.3.1 m-bus address register (madr) ............................................................... 7-6 7.3.2 m-bus frequency divider register (mfdr) ............................................... 7-6 7.3.3 m-bus control register (mbcr) ................................................................ 7-7 7.3.4 m-bus status register (mbsr) .................................................................. 7-9 7.3.5 m-bus data i/o register (mbdr)............................................................. 7-10 7.4 m-bus programming examples .................................................................. 7-10 7.4.1 initialization sequence.............................................................................. 7-10 7.4.2 generation of start ............................................................................... 7-11 7.4.3 post-transfer software response............................................................ 7-11 7.4.4 generation of stop ................................................................................. 7-12 7.4.5 generation of repeated start............................................................... 7-13 7.4.6 slave mode............................................................................................... 7-13 7.4.7 arbitration lost.......................................................................................... 7-13
table of contents xii mc68307 user? manual motorola section 8 serial module 8.1 module overview .......................................................................................... 8-2 8.1.1 serial communication channel .................................................................. 8-2 8.1.2 baud rate generator logic........................................................................ 8-3 8.1.3 baud rate generator/timer ....................................................................... 8-3 8.1.4 interrupt control logic ................................................................................ 8-3 8.1.5 comparison of serial module to mc68681................................................. 8-3 8.2 serial module signal definitions ................................................................... 8-3 8.2.1 transmitter serial data output (txd) ......................................................... 8-4 8.2.2 receiver serial data input (rxd) ............................................................... 8-4 8.2.3 request-to-send (rts )............................................................................. 8-4 8.2.4 clear-to-send (cts ) ................................................................................. 8-5 8.3 operation ...................................................................................................... 8-5 8.3.1 baud rate generator/timer ....................................................................... 8-5 8.3.2 transmitter and receiver operating modes............................................... 8-5 8.3.2.1 transmitter ............................................................................................... 8-6 8.3.2.2 receiver ................................................................................................... 8-8 8.3.2.3 fifo stack ............................................................................................... 8-8 8.3.3 looping modes ......................................................................................... 8-10 8.3.3.1 automatic echo mode ............................................................................ 8-10 8.3.3.2 local loopback mode ............................................................................ 8-11 8.3.3.3 remote loopback mode ........................................................................ 8-11 8.3.4 multidrop mode......................................................................................... 8-12 8.3.5 bus operation........................................................................................... 8-14 8.3.5.1 read cycles ........................................................................................... 8-14 8.3.5.2 write cycles ........................................................................................... 8-14 8.3.5.3 interrupt acknowledge cycles ................................................................ 8-14 8.4 register description and programming...................................................... 8-14 8.4.1 register description ................................................................................. 8-14 8.4.1.1 mode register 1 (umr1) ....................................................................... 8-15 8.4.1.2 mode register 2 (umr2) ....................................................................... 8-17 8.4.1.3 status register (usr) ............................................................................ 8-19 8.4.1.4 clock-select register (ucsr) ................................................................ 8-21 8.4.1.5 command register (ucr) ..................................................................... 8-23 8.4.1.6 receiver buffer (urb)............................................................................ 8-25 8.4.1.7 transmitter buffer (utb) ........................................................................ 8-25 8.4.1.8 input port change register (uipcr) ..................................................... 8-26 8.4.1.9 auxiliary control register (uacr) ......................................................... 8-26 8.4.1.10 interrupt status register (uisr) ............................................................ 8-27 8.4.1.11 interrupt mask register (uimr).............................................................. 8-28 8.4.1.12 timer upper preload register (ubg1)................................................... 8-29 8.4.1.13 timer upper preload register (ubg2)................................................... 8-29 8.4.1.14 interrupt vector register (uivr) ............................................................ 8-29 8.4.1.15 input port register (uip) ........................................................................ 8-29
table of contents motorola mc68307 user? manual xiii 8.4.1.16 output port data registers (uop1, uop0)............................................ 8-30 8.4.2 programming ............................................................................................ 8-30 8.4.2.1 serial module initialization ...................................................................... 8-31 8.4.2.2 i/o driver example ................................................................................. 8-31 8.4.2.3 interrupt handling ................................................................................... 8-31 8.5 serial module initialization sequence ......................................................... 8-31 section 9 ieee 1149.1 test access port 9.1 overview ....................................................................................................... 9-1 9.2 tap controller ............................................................................................... 9-3 9.3 boundary scan register ............................................................................... 9-4 9.4 instruction register ....................................................................................... 9-9 9.4.1 extest (0000) ........................................................................................ 9-10 9.4.2 sample/preload (0010)...................................................................... 9-10 9.4.3 bypass (1111) ........................................................................................ 9-10 9.4.4 clamp (1100) .......................................................................................... 9-11 9.5 mc68307 restrictions................................................................................. 9-11 9.6 non-ieee 1149.1 operation ....................................................................... 9-11 section 10 applications information 10.1 mc68307 minimum stand-alone system hardware .................................. 10-1 10.1.1 mc68307 signal configuration................................................................. 10-1 10.1.2 eprom memory interface........................................................................ 10-5 10.1.3 ram memory interface ............................................................................. 10-5 10.1.4 rs232 uart port .................................................................................... 10-5 10.1.5 eprom timing ......................................................................................... 10-6 10.1.6 ram timing .............................................................................................. 10-6 10.2 power management.................................................................................... 10-7 10.2.1 fully static operation ............................................................................... 10-7 10.2.2 prescalable cpu clock ............................................................................ 10-8 10.2.3 wake-up ................................................................................................... 10-8 10.2.4 low-power sleep mode............................................................................ 10-9 10.2.5 low-power stop mode ............................................................................. 10-9 10.3 using m-bus software to communicate between processor systems .... 10-10 10.3.1 overview of m-bus software transfer mechanism ................................ 10-11 10.3.2 m-bus master mode operation............................................................... 10-12 10.3.3 m-bus slave mode operation................................................................. 10-12 10.3.4 description of setup ............................................................................... 10-13 10.3.5 software flow ......................................................................................... 10-13 10.3.6 transfer blocks ....................................................................................... 10-14 10.3.7 software implementation ........................................................................ 10-14 10.3.7.1 software listing 1?-bus master software ........................................ 10-17 10.3.7.2 software listing 2?-bus slave software .......................................... 10-21
table of contents xiv mc68307 user? manual motorola 10.4 mc68307 uart driver examples ............................................................ 10-24 10.4.1 software listing 3 ................................................................................... 10-24 10.5 swapping rom and ram mapping on the mc68307 .............................. 10-27 10.5.1 software implementation........................................................................ 10-27 10.5.1.1 software listing 4 ................................................................................. 10-28 section 11 electrical characteristics 11.1 maximum ratings ....................................................................................... 11-1 11.2 thermal characteristics.............................................................................. 11-1 11.3 power considerations................................................................................. 11-2 11.4 ac electrical specification definitions ........................................................ 11-2 11.5 dc electrical specifications........................................................................ 11-4 11.6 ac electrical specifications?lock timing................................................ 11-4 11.7 ac electrical specifications?ead and write cycles................................ 11-5 11.8 ac electrical specifications?us arbitration............................................. 11-9 11.9 ac electrical specifications?051 bus interface module ....................... 11-11 11.10 timer module electrical characteristics ................................................... 11-13 11.11 uart electrical characteristics................................................................ 11-14 11.12 ac electrical characteristics?-bus input signal timing....................... 11-15 11.13 ac electrical characteristics?-bus output signal timing.................... 11-15 11.14 ac electrical characteristics?ort timing .............................................. 11-16 11.15 ieee 1149.1 electrical characteristics ..................................................... 11-17 section 12 ordering information and mechanical data 12.1 standard ordering information ................................................................... 12-1 12.2 100-pin pqfp pin assignments................................................................. 12-1 12.3 100-pin pqfp package dimensions.......................................................... 12-2 12.4 100-pin tqfp pin assignments ................................................................. 12-3 12.5 100-pin tqfp package dimensions .......................................................... 12-4 index
motorola mc68307 user? manual xv list of illustrations 1-1 mc68307 block diagram ................................................................................... 1-1 2-1 mc68307 detailed block diagram ..................................................................... 2-2 3-1 word read cycle flowchart (16-bit bus)........................................................... 3-2 3-2 byte read cycle flowchart (16-bit bus) ............................................................ 3-3 3-3 read and write cycle timing diagram (16-bit bus) .......................................... 3-3 3-4 word and byte read cycle timing diagram (16-bit bus).................................. 3-4 3-5 word write cycle flowchart (16-bit bus)........................................................... 3-5 3-6 byte write cycle flowchart (16-bit bus) ............................................................ 3-6 3-7 word and byte write cycle timing diagram...................................................... 3-6 3-8 read-modify-write cycle flowchart................................................................... 3-8 3-9 read-modify-write cycle timing diagram ......................................................... 3-9 3-10 interrupt acknowledge cycle ?address bus ................................................... 3-11 3-11 interrupt acknowledge cycle timing diagram ................................................. 3-12 3-12 8051-compatible read cycle signals.............................................................. 3-14 3-13 8051-compatible write cycle signals.............................................................. 3-14 3-14 three-wire bus arbitration cycle flowchart .................................................... 3-15 3-15 two-wire bus arbitration cycle flowchart....................................................... 3-16 3-16 three-wire bus arbitration timing diagram .................................................... 3-17 3-17 two-wire bus arbitration timing diagram ....................................................... 3-17 3-18 external asynchronous signal synchronization............................................... 3-19 3-19 bus arbitration unit state diagrams................................................................. 3-20 3-20 three-wire bus arbitration timing diagram?rocessor active...................... 3-21 3-21 three-wire bus arbitration timing diagram?us inactive ............................. 3-22 3-22 three-wire bus arbitration timing diagram?pecial case............................ 3-23 3-23 two-wire bus arbitration timing diagram?rocessor active ........................ 3-24 3-24 two-wire bus arbitration timing diagram?us inactive................................ 3-25 3-25 two-wire bus arbitration timing diagram?pecial case .............................. 3-26 3-26 bus error timing diagram................................................................................ 3-28 3-27 retry bus cycle timing diagram ..................................................................... 3-29 3-28 halt operation timing diagram........................................................................ 3-30 3-29 reset operation timing diagram..................................................................... 3-32 3-30 fully asynchronous read cycle ...................................................................... 3-33 3-31 fully asynchronous write cycle....................................................................... 3-33 3-32 pseudo-asynchronous write cycle.................................................................. 3-34 3-33 pseudo-asynchronous read cycle.................................................................. 3-34 3-34 synchronous read cycle................................................................................. 3-37 3-35 synchronous write cycle ................................................................................. 3-37 4-1 programming model ........................................................................................... 4-2 4-2 status register................................................................................................... 4-3 thi d t t d ith f m k 4 0 4
list of illustrations xvi mc68307 user? manual motorola 4-3 general form of exception stack frame......................................................... 4-10 4-4 general exception processing flowchart ........................................................ 4-11 4-5 exception vector format.................................................................................. 4-12 4-6 address translated from 8-bit vector number ................................................ 4-12 4-7 supervisor stack order for bus or address error exception ........................... 4-19 5-1 module base address, decode logic ................................................................ 5-3 5-2 chip-select block diagram ................................................................................ 5-6 5-3 external bus interface logic .............................................................................. 5-9 5-4 interrupt controller logic block diagram ......................................................... 5-15 6-1 timer block diagram.......................................................................................... 6-2 7-1 m-bus interface block diagram ......................................................................... 7-2 7-2 m-bus transmission signals.............................................................................. 7-3 7-3 m-bus clock synchronization ............................................................................ 7-5 7-4 flow-chart of typical m-bus interrupt routine ................................................ 7-14 8-1 simplified block diagram ................................................................................... 8-1 8-2 external and internal interface signals .............................................................. 8-4 8-3 baud rate generator block diagram................................................................. 8-5 8-4 transmitter and receiver functional diagram................................................... 8-6 8-5 transmitter timing diagram............................................................................... 8-7 8-6 receiver timing diagram................................................................................... 8-9 8-7 looping modes functional diagram ................................................................ 8-11 8-8 multidrop mode timing diagram ...................................................................... 8-13 8-9 serial mode programming flowchart............................................................... 8-32 9-1 test access port block diagram........................................................................ 9-2 9-2 tap controller state machine............................................................................ 9-3 9-3 output cell (o.cell)............................................................................................ 9-6 9-4 input cell (i.cell) ................................................................................................ 9-7 9-5 output control cell (en.cell).............................................................................. 9-7 9-6 bidirectional cell (io.cell) .................................................................................. 9-8 9-7 bidirectional cell (iox0.cell) .............................................................................. 9-8 9-8 general arrangement for bidirectional pins....................................................... 9-9 9-9 bypass register ............................................................................................... 9-10 10-1 mc68307 minimum system configuration....................................................... 10-3 10-2 hardware setup ............................................................................................. 10-13 10-3 master/slave responsibilities for the master transmit block ........................ 10-15 10-4 summary of m-bus activity for the master transmit block ............................ 10-15 10-5 master/slave responsibilities for the master receive block ......................... 10-16 10-6 summary of m-bus activity for the master receive block ............................. 10-16 10-7 memory map after swap complete................................................................ 10-28 11-1 drive levels and test points for ac specifications ......................................... 11-3 11-2 clock timing .................................................................................................... 11-5 11-3 read cycle timing diagram ............................................................................ 11-7 11-4 write cycle timing diagram ............................................................................ 11-8 11-5 three-wire bus arbitration diagram ................................................................ 11-9 11-6 two-wire bus arbitration timing diagram..................................................... 11-10
list of illustrations motorola mc68307 user? manual xvii 11-7 external 8051 bus read cycle ...................................................................... 11-12 11-8 external 8051 bus write cycle....................................................................... 11-12 11-9 timer module timing diagram ....................................................................... 11-13 11-10 transmitter timing ......................................................................................... 11-14 11-11 receiver timing ............................................................................................. 11-14 11-12 m-bus interface input/output signal timing .................................................. 11-15 11-13 port timing ..................................................................................................... 11-16 11-14 test clock input timing diagram ................................................................... 11-17 11-15 boundary scan timing diagram .................................................................... 11-18 11-16 test access port timing diagram.................................................................. 11-18
motorola mc68307 user? manual xix list of tables 2-1 68000 bus signal summary............................................................................... 2-3 2-2 8051 bus signal summary................................................................................. 2-3 2-3 chip select signal summary.............................................................................. 2-3 2-4 interrupt port signal summary ........................................................................... 2-4 2-5 clock and mode control signal summary ......................................................... 2-4 2-6 serial module signal summary .......................................................................... 2-4 2-7 jtag signal summary....................................................................................... 2-4 2-8 timer module signal summary .......................................................................... 2-5 2-9 m-bus module signal summary......................................................................... 2-5 2-10 data strobe control of data bus........................................................................ 2-8 2-11 signal index...................................................................................................... 2-14 4-1 processor data formats .................................................................................... 4-3 4-2 effective addressing modes............................................................................... 4-4 4-3 notation conventions ......................................................................................... 4-4 4-4 ec000 core instruction set summary ............................................................... 4-6 4-5 exception vector assignments......................................................................... 4-13 4-6 exception grouping and priority....................................................................... 4-19 5-1 address block selection in peripheral chip select mode .................................. 5-7 5-2 port a pin functions......................................................................................... 5-12 5-3 port b pin functions......................................................................................... 5-12 5-4 interrupt vector response ............................................................................... 5-16 5-5 mc68307 configuration memory map ............................................................. 5-20 5-6 dtack field encoding .................................................................................... 5-32 7-1 m-bus prescaler values..................................................................................... 7-7 8-1 serial module programming model .................................................................. 8-15 8-2 pmx and pt control bits .................................................................................. 8-16 8-3 b/cx control bits .............................................................................................. 8-17 8-4 cmx control bits .............................................................................................. 8-17 8-5 sbx control bits ............................................................................................... 8-18 8-6 rcsx control bits ............................................................................................ 8-21 8-7 tcsx control bits............................................................................................. 8-22 8-8 miscx control bits ........................................................................................... 8-23 8-9 tcx control bits ............................................................................................... 8-24 8-10 rcx control bits............................................................................................... 8-24 8-11 timer mode and source select bits................................................................. 8-27 9-1 boundary scan control bits ............................................................................... 9-4 9-2 boundary scan bit definitions............................................................................ 9-5 9-3 instructions ......................................................................................................... 9-9 10-1 power contribution from modules .................................................................... 10-7 thi d t t d ith f m k 4 0 4
motorola mc68307 user? manual 1-1 section 1 introduction the mc68307 is an integrated processor combining a static ec000 processor with multiple interchip bus interfaces. the mc68307 is designed to provide optimal integration and performance for applications such as digital cordless telephones, portable measuring equipment, and point-of-sale terminals. by providing 3.3 v, static operation in a small package, the mc68307 delivers cost-effective performance to handheld, battery-powered applications. the mc68307 (see figure 1-1) contains a static ec000 core processor, multiple bus interfaces, a serial channel, two timers, and common system glue logic. the multiple bus interfaces include: dynamic 68000 bus, 8051-compatible bus, and motorola bus (m-bus) or i 2 c bus 1 . the dynamically-sized 68000 bus allows 16-bit performance using static random access memory (sram) while providing a low-cost interface to an 8-bit read-only memory (rom). the 8051-compatible bus interfaces gluelessly to 8051-type devices and allows the reuse 1. i 2 c bus is a proprietary philips interface bus. figure 1-1. mc68307 block diagram processor control and clock 68000 internal bus 8/16-bit m68000 bus interface interrupt controller dual timer module uart serial i/o m-bus module static ec000 core processor dynamic bus sizing extension system integration module (sim07) 8051 bus interface chip select and dtack parallel i/o ports system protection power management jtag port thi d t t d ith f m k 4 0 4
introduction 1-2 mc68307 user? manual motorola of application-specific integrated circuits (asics) designed for this industry standard bus. the m-bus is an industry-standard 2-wire interface that provides efficient communications with peripherals such as eeprom, analog/digital (a/d) converters, and liquid crystal display (lcd) drivers. thus, the mc68307 interfaces gluelessly to boot rom, sram, 8051 devices, m-bus devices, and memory-mapped peripherals. the mc68307 also incorporates a slave mode which allows the ec000 core to be disabled, providing a 3.3-v or 5-v static, low-power multifunction peripheral for higher performance m68000 family processors. the main features of the mc68307 include: static ec000 core processor full compatibility with m68000 and ec000 24-bit address bus, for 16-mbyte off-chip address space 16-bit on-chip data bus for m68000 bus operations 2.7 mips performance at 16.67 mhz processor clock processor disable mmode for use as a peripheral to an external processor emulation mode for use with in-circuit emulator external m68000 bus interface with dynamic bus sizing for 8-bit and 16-bit data ports external 8051-compatible 8-bit data bus interface power management fully static operation with processor shutdown and wake-up modes for substatial power savings very rapid response to interrupts from the power-down state operates from dc to 16.67 mhz system clock clock enable/disable for each peripheral m-bus module provides interchip bus interface for eeproms, lcd controllers, a/d converters, etc. compatible with industry-standard i 2 c bus master or slave operation modes, supports multiple masters automatic interrupt generation with programmable level software-programmable clock frequency data rates from 4?00 kbit/s above 3.0 mhz system clock universal asynchronous receiver/transmitter (uart) module flexible baud rate generator based on mc68681 dual universal asynchronous receiver/transmitter (duart) programming model 5 mbits/s maximum transfer rate at 16.67 mhz system clock automatic interrupt generation with programmable level modem control signals available (cts , rts ) timer module dual channel 16-bit general-purpose counter/timer multimode operation, independent capture/compare registers automatic interrupt generation with programmable level 60-ns resolution at 16.67 mhz system clock separate input and output pins for each timer
introduction motorola mc68307 user? manual 1-3 system integration module (sim07), incorporating many functions typically relegated to external programmable array logic (pals), transistor-transistor logic (ttl), and asics, such as: ?ystem configuration, programmable address mapping ?ystem protection by hardware watchdog logic and software watchdog timer ?ower-down mode control, programmable processor clock driver ?our programmable chip selects with wait state generation logic ?hree simple peripheral chip selects ?arallel input/output ports, some with interrupt capability ?rogrammed interrupt vector response for on-chip peripheral modules ?eee 1149.1 boundary scan test access port (jtag) operating voltages of 3.3v 0.3v and 5v 0.5v 0 to 70 c (standard part); ?0 to +85 c (extended temperature part) compact 100-lead quad flat pack (qfp) and 100-lead thin quad flat pack (tqfp) packages 1.1 m68300 family the mc68307 is one of a series of components in motorola's m68300 family. other mem- bers of the family include the mc68302, mc68306, mc68322, mc68330, mc68331, mc68332, mc68f333, mc68334, mc68340, mc68341, mc68349, mc68356, and mc68360. 1.1.1 organization the m68300 family of integrated processors and controllers is built on an m68000 core pro- cessor and a selection of intelligent peripherals appropriate for a set of applications. com- mon system glue logic such as address decoding, wait state insertion, interrupt prioritization, and watchdog timing is also included. each member of the m68300 family is distinguished by its selection of on-chip peripherals. peripherals are chosen to address specific applications, but are often useful in a wide variety of applications. the peripherals may be highly sophisticated timing or protocol engines that have their own processors, or they may be more traditional peripheral functions, such as uarts and timers. 1.1.2 advantages by incorporating so many major features into a single m68300 family chip, a system designer can realize significant savings in design time, power consumption, cost, board space, pin count, and programming. the equivalent functionality can easily require 20 sep- arate components. each component might have 16?4 pins, totalling over 350 connections. most of these connections require interconnects or are duplications. each connection is a candidate for a bad solder joint or misrouted trace. each component is another part to qual- ify, purchase, inventory, and maintain. each component requires a share of the printed cir- cuit board. each component draws power, which is often used to drive large buffers to get the signal to another chip. the cumulative power consumption of all the components must be available from the power supply. the signals between the central processing unit (cpu)
introduction 1-4 mc68307 user? manual motorola and a peripheral might not be compatible nor run from the same clock, requiring time delays or other special design considerations. in an m68300 family component, the major functions and glue logic are all properly con- nected internally, timed with the same clock, fully tested, and uniformly documented. only essential signals are brought out to pins. the primary package is the surface-mount plastic qfp for the smallest possible footprint. 1.2 mc68307 architecture to improve total system throughput and reduce part count, board size and cost of system implementation, the mc68307 integrates a powerful processor, intelligent peripheral mod- ules, and typical system interface logic. these functions include the sim07, timers, uart, m-bus interface, and 8051-compatible bus interface. the ec000 core processor communicates with these modules via an internal bus, providing the opportunity for fully synchronized communication between all modules and allowing interrupts to be handled in parallel with data transfers, greatly improving system perfor- mance. 1.2.1 ec000 core processor the ec000 is a core implementation of the m68000 32-bit microprocessor architecture. the programmer can use any of the eight 32-bit data registers for fast manipulation of data and any of the eight 32-bit address registers for indexing data in memory. flexible instructions support data movement, arithmetic functions, logical operations, shifts and rotates, bit set and clear, conditional and unconditional program branches, and overall system control. the ec000 core can operate on data types of single bits, binary-coded decimal (bcd) digits, and 8, 16, and 32 bits. the integrated chip selects allow peripherals and data in memory to reside anywhere in the 16-mbyte linear address space. a supervisor operating mode pro- tects system-level resources from the more restricted user mode, allowing a true virtual envi- ronment to be developed. many addressing modes complement these instructions, including predecrement and postincrement, which allow simple stack and queue mainte- nance and scaled indexing for efficient table accesses. data types and addressing modes are supported orthogonally by all data operations and with all appropriate addressing modes. position-independent code is easily written. like all m68000 family processors, the ec000 core recognizes interrupts of seven different priority levels and, in conjunction with the integrated interrupt controller, allows a pro- grammed vector to direct the processor to the desired service routine. internal trap excep- tions ensure proper instruction execution with good addresses and data, allow operating system intervention in special situations, and permit instruction tracing. the hardware time- out can terminate bad memory accesses before instructions process data incorrectly. the ec000 core provides 2.7 millions of bits per second (mips) at 16.67 mhz. 1.2.2 system integration module (sim07) the sim07 provides the external bus interface for the ec000 core. it also eliminates much of the glue logic that typically supports a microprocessor and its interface with the peripheral
introduction motorola mc68307 user? manual 1-5 and memory system. the sim07 provides programmable circuits to perform address-decod- ing and chip selects, wait-state insertion, interrupt handling, clock generation, discrete i/o, and power management features. 1.2.2.1 external bus interface. the external bus interface (ebi) handles the trans- fer of information between the internal ec000 core and memory, peripherals, or other pro- cessing elements in the external address space. it consists of an m68000 bus interface and an 8051-compatible bus interface. the external m68000 bus provides up to 24 address lines and 16 data lines. each bus access can appear externally either as an m68000 bus cycle (either 16-bit or 8-bit dynamic data bus width) or an 8-bit wide 8051-compatible bus cycle (multiplexing address and 8-bit data) with the respective sets of control signals. the default bus cycle is an m68000 16-bit-wide one, the 8051-compatible address space being pro- grammable. 1.2.2.2 chip select and wait state generation. four programmable chip select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing. base memory address and block size are both programmable, with some restrictions, (e.g. a starting address must be on a boundary which is a multiple of the block size). each chip- select is general-purpose. however one of the chip-selects can be programmed to select an addressing range which is decoded as an 8051-compatible bus access, and another can be used to enable one of four simple external peripherals. data bus width (8-bit or 16-bit) is pro- grammable on all four chip-selects and further decoding is available for protection from user mode access or read-only access. 1.2.2.3 system configuration and protection. the sim07 provides configura- tion registers that allow general system functions to be controlled and monitored. for exam- ple, all on-chip registers can be relocated as a block by programming a module base address, power-down modes can be selected, and the source of the most recent reset or berr can be checked. the hardware watchdog features can be enabled or disabled and the bus timeout times can be programmed. the power-down mode allows software to disable the ec000 core during periods of inactiv- ity. this feature works in conjunction with the interrupt control logic to allow any interrupt condition to cause a wake-up, which causes the ec000 core to resume processing without requiring any reset or re-initialization. all register contents are preserved, and the inter- rupt which caused wake-up is serviced in the normal manner as soon as the clock restarts. to reduce power consumption further, the internal clocks to the on-chip peripheral modules can be disabled by software. 1.2.2.4 parallel input/output ports. two general-purpose ports (a and b) are provided for input/output, although the pins for these ports are shared with other functions. some bits in port a are multiplexed with the peripheral chip-select lines and timer output sig- nals, and port b is multiplexed with various peripheral i/o lines from the uart, m-bus and timer modules. maximum flexibility is therefore available for differing hardware configura- tions. eight of the 16 port b lines are also latched inputs to the interrupt controller, with pro- grammable interrupt priority level.
introduction 1-6 mc68307 user? manual motorola 1.2.2.5 interrupt controller. the sim07 coordinates all interrupt sources, both from on-chip peripherals (timer1, timer2, m-bus, and uart) and off-chip inputs (irq7 , and int1 ?nt8 ). it provides interrupt requests to the ec000 core with programmable priority level, and responds to acknowledge cycles by providing programmed vectors unique to each source. 1.2.3 timer module the timer module comprises two independent, identical general-purpose timers, and a soft- ware watchdog timer. each general-purpose timer block contains a free-running 16-bit timer that can be used in various modes, to capture the timer value with an external event, to trig- ger an external event or interrupt when the timer reaches a set value, or to count external events. each has an 8-bit prescaler to allow a programmable clock input frequency derived from the system clock or external count input. the output pins (one per timer) have a pro- grammable mode. a software watchdog timer is also provided for system protection. if required, this resets the ec000 core if it is not refreshed periodically by software. 1.2.4 uart module the mc68307 contains a full-duplex uart module, with an on-chip baud-generator provid- ing both standard and nonstandard baud rates up to 5 mb/s. the module is functionally equivalent to the mc68681 duart, although only one serial channel is implemented. data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and up to two stop bits in 1/16 increments. four-byte receive buffers and two-byte transmit buffers minimize cpu service calls. a wide variety of error detection and maskable interrupt capability is provided on each channel. full-duplex autoecho loopback, local loopback, and remote loopback modes can be selected. multidrop applications are supported. clocking is provided by the mc68307 system clock, via a programmable prescaler allowing various baud rates to be chosen. modem support is provided with request-to-send (rts ) and clear-to-send (cts ) lines available. the serial port can sustain data rates of 5 mbps. 1.2.5 m-bus module the m-bus interface module provides a two-wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices. it is compatible with the i 2 c-bus standard. m-bus minimizes the interconnection between devices in the end-system. it is best suited for applications which need occasional bursts of fast communication over a short distance, among a number of devices. the maximum data rate is limited to 595 kbps at 16.67 mhz (100 kbps to be compatible with i 2 c), the maximum communication length and number of devices which can be connected are limited physically by the maximum bus capacitance and logically by the number of unique addresses. the m-bus system is a true multimaster bus including collision detection and arbitration to prevent data corruption if two or more masters intend to control the bus simultaneously. this feature provides the capability for complex applications with multiprocessor control. it may also be used for rapid testing and alignment of end products via external diagnostic connec- tions.
introduction motorola mc68307 user? manual 1-7 1.2.6 test access port to aid in system diagnostics, the mc68307 includes dedicated user-accessible test logic that is compliant with the ieee 1149.1 standard for boundary scan testability, often referred to as jtag (joint test action group). this is described briefly in section 9 ieee 1149.1 test access port . for further information refer to the ieee 1149.1 standard.
motorola mc68307 user? manual 2-1 section 2 signal description this section contains a brief description of the input and output signals, with reference (if applicable) to other sections which give greater detail on its use. figure 2-1 provides a detailed diagram showing the integrated peripherals and signals, and table 2-2 to table 2- 9 provide a quick reference for determining a signal's name, mnemonic, its use as an input or output, active state, and type identification. note the terms assertion and negation will be used extensively. this is done to avoid confusion when dealing with a mixture of ?ctive-low?and ?ctive-high?signals. the term assert or asser- tion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. the term negate or negation is used to indicate that a signal is inac- tive or false. thi d t t d ith f m k 4 0 4
signal description 2-2 mc68307 user? manual motorola . figure 2-1. mc68307 detailed block diagram 16-bit 68000 internal bus tdo tdi tms tck cs2b /pa0 multiplexed parallel i/o multiplexed parallel i/o system integration module (sim07) 8-/16-bit 68000 bus interface 8051 bus interface chip and dtack processor control, clock and low power m-bus (i2c) module uart serial i/o dual timer module static ec000 core processor dynamic bus sizing extension vcc gnd 6 6 extal xtal clkout scl/pb0 sda/pb1 cts /pb5 rts /pb4 rxd/pb3 txd/pb2 tin1/pb6 tin2/pb7 cs2c /pa1 cs2d /pa2 tout1 /pa3 tout2 /pa4 br /pa5 bg /pa6 bgack /pa7 as uds lds r/w dtack d15?0 a23?8 ad7?d0 /a7?0 rd wr ale cs3 cs2 /cs2a cs1 cs0 busw0 irq7 reset halt rstin int1 /pb8 int2 /pb9 int3 /pb10 int4 /pb11 int5 /pb12 int6 /pb13 int7 /pb14 int8 /pb15 jtag port select interrupt controller
signal description motorola mc68307 user? manual 2-3 table 2-1. 68000 bus signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required address signals a23?0 output yes (4) address strobe as output yes (3) bus grant bg /pa6 output (2) no bus grant acknowledge bgack /pa7 input (2) (1) bus request br /pa5 input (2) (1) data bus d15?0 i/o yes data transfer acknowledge dtack i/o yes 2.2 k w halt halt i/o 2.2 k w lower data strobe lds output yes (3) upper data strobe uds output yes (3) read/write r/w output yes (3) reset reset i/o 2.2 k w table 2-2. 8051 bus signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required address/data bus ad7?d0 i/o yes address latch enable ale output no 8051 read strobe rd output no 8051 write strobe wr output no notes: 1. pullup may be required (value depends on individual application). this pin must not be left ?ating. 2. these signals have dual functions as port a i/o lines. their function is programmed in the port a control register. 3. a pull-up is required if the output is decoded, otherwise leave unconnected. (value of pull-up resistor depends on individual application. 4. a pull-up is required on a23 if it is decoded. pull-ups on whole bus minimize sleep mode power consumption. table 2-3. chip select signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required chip select cs3 ?s0 output no peripheral chip select cs2d /pa0, cs2c / pa1, cs2b /pa2 output (1) no note: 1. these signals have dual functions as port a i/o lines. their function is programmed in the port a control register.
signal description 2-4 mc68307 user? manual motorola table 2-4. interrupt port signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required interrupt request level 7 irq7 input (1) latched interrupt 1 int1 /pb8 input (2) (1) latched interrupt 2 int2 /pb9 input (2) (1) latched interrupt 3 int3 /pb10 input (2) (1) latched interrupt 4 int4 /pb11 input (2) (1) latched interrupt 5 int5 /pb12 input (2) (1) latched interrupt 6 int6 /pb13 input (2) (1) latched interrupt 7 int7 /pb14 input (2) (1) latched interrupt 8 int8 /pb15 input (2) (1) notes: 1. pullup or pulldown may be required (value depends on individual application). 2. these signals have dual functions as port b i/o lines. their function is programmed in the port b control register. table 2-5. clock and mode control signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required crystal oscillator or external clock extal input crystal oscillator xtal output system clock clkout output no initial bus width for cs0 busw0 input power-on reset rstin input (1) note: 1. pullup may be required (value depends on individual application). this pin must not be left ?ating. table 2-6. serial module signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required uart transmitter serial data txd/pb2 output (1) no uart receiver serial data rxd/pb3 input (1) uart request-to-send rtsa /pb4 output (1) no uart clear-to-send ctsa /pb5 input (1) (2) notes: 1. these signals have dual functions as port b i/o lines. their function is programmed in the port b control register. 2. pullup may be required (value depends on individual application). if used as ctsa this pin must not be left ?ating. table 2-7. jtag signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required test clock tck input test data input tdi input test data output tdo output test mode select tms input
signal description motorola mc68307 user? manual 2-5 2.1 bus signals the following signals are used for the mc68307 bus. 2.1.1 address bus (a23?0) the address bus signals are outputs that define the address of a byte (or the most significant byte) to be transferred during a bus cycle. the mc68307 places the address on the bus at the beginning of a bus cycle, it is valid while the address strobe output (as ) is asserted. the complete address bus (a23?0) is capable of addressing 16 mbytes of data. the address bus signals are three-stated when the mc68307 is arbitrated off the bus by an external bus master. they are also three-stated during reset of the ec000 core. the address bus consists of the following groups of signals. refer to section 3 bus oper- ation for information on the address bus and its relationship to bus operation. 2.1.1.1 address bus (a23?8). these signals are always used as address output lines. they are valid when address strobe (as ) is asserted. chip-selected memory and peripher- als, including 8051-compatible bus devices, need not decode the upper address bits, depending on the programmed block size for that chip select. 2.1.1.2 address bus (ad7?d0). in addition to carrying eight address signals a7?0, these low-order address lines also carry the 8-bit data bus during 8051-compatible bus cycles, as indicated by the relevant strobe signals (rd and wr ). at the start of each type of bus cycle (both m68000 and 8051-compatible), they carry the eight low-order address bits a7?0. in m68000 bus cycles, they are valid addresses when address strobe (as ) is asserted. chip select 3 (cs3 ) should be used to distinguish 8051 bus cycles if necessary. table 2-8. timer module signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required timer input 1 tin1/pb6 input (1) (2) timer input 2 tin2/pb7 input (1) (2) timer output 1 tout1/pa3 output (1) timer output 2 tout2/pa4 output (1) notes: 1. these signals have dual functions as port a and port b i/o lines. their function is programmed in the port a or port b control register. 2. pullup may be required (value depends on individual application). if used as timer inputs, these pins must not be left ?ating. table 2-9. m-bus module signal summary signal name mnemonic input/ output three-state during bus arbitration pullup resistor required m-bus clock scl/pb0 i/o (1) 2.2 k w m-bus data sda/pb1 i/o (1) 2.2 k w note: 1. these signals have dual functions as port b i/o lines. their function is programmed in the port b control register.
signal description 2-6 mc68307 user? manual motorola address line a0 is included for 8-bit data-bus interfaces only, i.e., the 8051-compatible bus, as described above, and also the dynamically-sized 68000 bus when programmed to use an 8-bit data-bus width. during 16-bit data-bus width cycles, the a0 output is meaningless, and should be ignored, as it may well hold a misleading value. the uds and lds signals should be used to further decode the even/odd byte access in this case. 2.1.2 data bus (d15?0) this 16-bit bidirectional parallel bus contains the data being transferred to or from the mc68307 during m68000 bus cycles. its value should be ignored during 8051-compatible bus read and write cycles, it is not three-stated in either case. a read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. during an internal peripheral access, the data bus reflects the value read or written, for emu- lation and debug purposes. care is required, therefore, if external buffers are needed. the data bus has a programmable 8-bit bus size option for m68000 bus cycles, which is used in conjunction with the programmable chip-select dynamic bus sizing. if a chip select is configured for 8-bit port size, any 16-bit transfers appears externally as two 8-bit transfers. in this case, the 8-bit data uses the d15?8 lines only. 2.2 chip selects the programmable chip select outputs allow system designers to interface the mc68307 directly to memory and peripheral devices without having to perform address decode requir- ing additional external logic. although they can be programmed for many different configu- rations, each one has a particular usage to which it is tailored, giving added functionality. they are asserted coincident with the address strobe (as ) output, and are all active-low. refer to section 5 system integration module for details of how the chip selects can be programmed. 2.2.1 chip select 0 (cs0 ) this signal is the chip select for a boot rom containing the reset vectors and initialization program. from a cold reset, this chip select is asserted on every bus cycle in the first 8k bytes of address space until is is programmed otherwise. the busw0 pin specifies how this chip select behaves from cold reset, whether it is an 8-bit wide data bus access (busw0=0) or a 16-bit wide data bus access (busw0=1). 2.2.2 chip select 1 (cs1 ) this signal is primarily intended to be an enable for a ram memory device. from a cold reset, this signal does not assert until it is programmed with a valid base address and address mask. the data bus width for memory devices selected by this chip select is also programmable, between 8- and 16-bit data, in the system control register. 2.2.3 chip select 2 (cs2 , cs2b , cs2c , cs2d ) although the cs2 /cs2a pin can be used as a general-purpose m68000 chip-select (cs2 ), it can, together with the cs2b , cs2c, cs2d signals, be used to enable one of four miscel- laneous peripherals. the cs2 output address range can be relocated like any of the other
signal description motorola mc68307 user? manual 2-7 chip selects by programming, but it has the three extra enable outputs which are used to further divide this address space. if they are used, each of the four peripheral enable outputs decode fixed 16-kbyte address ranges within the confines of the programmed range of cs2 (which should therefore be a block 64k bytes in size). refer to section 5.1.2.2 peripheral chip selects and section 5.2.2 chip select registers for details. the data bus width for memory devices selected by this chip select is programmable, between 8- and 16-bit data, in the system control register. the cs2 /cs2a chip select signal has its own pin on the mc68307, but the three extra enable outputs cs2b , cs2c , cs2d are multiplexed with the port a input/output functions, and require to be programmed to use these pins at cold reset. this is done by setting bits in the port a control register (pacnt) as well as a bit in the system control register to enable the peripheral address decoder. as port a defaults to an input port on cold reset, these three additional peripheral chip select lines, if they are used, should have pullup resistors to ensure peripherals are not accidentally enabled during system initialization. when programmed as general-purpose input/output port lines, cs2b ? s2d function as pa0?a2. 2.2.4 chip select 3 (cs3 ) this chip select output can be programmed to perform an 8051-compatible bus cycle rather than a m68000 bus cycle. if 8051-compatible bus access is not required in a design, then this signal can be programmed to be a general purpose chip-select output. the data bus width for m68000-bus memory devices selected by this chip select is programmable, between 8- and 16-bit data, in the system control register. if the 8051-compatible bus inter- face is enabled, then the data-bus width for this chip select should be programmed to be 8 bits. the 8051-compatible bus has an address space (typically 64 kbytes long, but not restricted) which can be located anywhere in memory, as long as it does not overlap with other programmed chip select ranges. 2.3 bus control signals these are signals that may be decoded or provided by external logic, to control the various types of bus access which can occur. the bus control signals are three-stated whenever the mc68307 is arbitrated off the bus by an external bus master. 2.3.1 data transfer acknowledge (dtack ) this bidirectional, open-drain, active-low signal indicates that the data transfer has been completed. dtack is an output when it is generated internally by the programmable wait- state generators in the chip-select logic (including cs3 for 8051-compatible bus accesses), or during an access to internal peripheral registers. it is an input for all other m68000 bus cycles, i.e., when the mc68307 accesses an external device not within the range of the chip- select logic or when programmed to be generated externally for any particular chip-select. in this case, external logic must assert it in order to complete the bus cycle.
signal description 2-8 mc68307 user? manual motorola 2.3.2 address strobe (as ) this three-state active-low output signal indicates that there is a valid address on the address bus during m68000 bus cycles. it should be ignored during 8051-compatible bus cycles as the eight low-order address lines also carry the data bus during such a cycle. dur- ing all types of bus cycle, it should be taken into account when other bus masters are arbi- trating for the bus, as it indicates that the mc68307 is still using the bus. when the bus is arbitrated to an external master, or during reset, as is three-stated. 2.3.3 read/write (r/w ) this three-state output signal defines the data-bus transfer as a read or a write cycle. the r/w signal relates to the data strobe signals described in the following paragraphs. when the r/w line is high, the processor reads from the data bus. when the r/w line is low, the processor drives the data bus. the processor also drives the data bus during a read from an internal location, to aid emulation and debug. when the bus is arbitrated to an external master, or during reset, r/w is three-stated. 2.3.4 data strobes, upper and lower (uds , lds ) these three-state active-low output signals control the flow of data on the m68000 data bus. table 2-10 lists the combinations of these signals and the corresponding data on the bus in 16-bit wide mode. in 8-bit wide bus mode (programmed in conjunction with chip selects), all bus cycles appear as 8-bit reads or writes to the upper half of the data bus (d15?8), and so uds only is asserted. a0 should be used to determine even or odd byte being addressed in this case; it is valid whenever the external as signal is asserted during such a cycle. there is no external indication of data-bus width other than the chip-select asserted. the user has the knowledge of what bus width that chip-select is programmed to provide, for any given configuration of the mc68307 in a system. table 2-10. data strobe control of data bus uds lds r/w d15?8 d7?0 high high no valid data no valid data low low high valid data bits 15? valid data bits 7? high low high no valid data valid data bits 7? low high high valid data bus 15? no valid data low low low valid data bits 15? valid data bits 7? high low low valid data bits 7? valid data bits 7? low high low valid data bits 15? valid data bits 15?
signal description motorola mc68307 user? manual 2-9 when the bus is arbitrated to an external master, or during reset, uds and lds are three- stated. d7?0 should be regarded as invalid in 8-bit-wide bus mode. 2.3.5 8051 address latch enable (ale) this output signal is used to latch the low byte of address (ad7?d0 signals) during access to external 8051-compatible peripheral circuits. its function is tied to cs3 logic which can be programmed to locate the 8051-compatible bus address space anywhere in the memory map. for a discussion of the timing of the 8051-compatible bus signals, refer to section 3 bus operation . ale is not three-stated during external bus mastership or system reset. 2.3.6 8051-compatible bus read (rd ) this active-low output indicates that the bus cycle in progress is an 8051 read cycle, and that an addressed 8051 peripheral should provide data on the ad7?d0 lines within the specified access time. rd is not three-stated during external bus mastership or system reset. 2.3.7 8051-compatible bus write (wr ) this active-low output indicates that the bus cycle in progress is an 8051 write cycle, and that an addressed 8051 peripheral should accept the valid data which is now on the ad7-ad0 lines. wr is not three-stated during external bus mastership or system reset. 2.3.8 bus width select for cs0 (busw0) the state on this input pin is read at reset, and is used to choose the data bus width for mem- ory accesses for cs0 (refer to section 5.2.1.2 system control register (scr) ). hold busw0 low for an 8-bit data bus, or high for a 16-bit data bus during bus cycles which trigger cs0 . busw0 does not choose the bus width for cs1 , cs2 or cs3 ; that is done by user ini- tialization code. internally, the mc68307 always has a 16-bit bus. 2.4 exception control signals the following paragraphs describe the exception control signals. 2.4.1 reset (reset ) the external assertion of this bidirectional active-low signal simultaneously with the asser- tion of halt starts a system initialization sequence by resetting the whole mc68307 (pro- cessor, sim, and internal peripherals). this is called a cold reset or system reset. the processor assertion of reset (from executing a reset instruction) resets all external devices of a system and internal peripherals of the mc68307 without affecting the initial state of the processor, chip select logic, port configuration, or interrupt configuration. this is called a software reset or peripheral reset. refer to section 3 bus operation for further information on reset operation. during a cold reset, the address bus, data bus, and bus control pins (as , uds , lds , r/w ) are all three-stated. chip select outputs, cs3 ? s0 , remain high. none of these signals are three-stated during a peripheral reset.
signal description 2-10 mc68307 user? manual motorola 2.4.2 power-on reset (rstin ) this active-low input signal causes the mc68307 (processor, sim, and peripherals) to enter the reset state (cold reset). the assertion of rstin causes reset to be asserted out to reset external circuitry; however, note that halt is not asserted as a result of rstin asser- tion. internal power-on reset circuitry provides a reset pulse of at least 32768 clocks width at power-on or when rstin is subsequently asserted. this reset pulse length can be extended by adding an external rc network, to ensure that rstin is held low for long enough to apply the reset pulse for 128 cpu clocks after v cc and clock are stable. refer to section 10.1 mc68307 minimum stand-alone system hardware for an example circuit. 2.4.3 halt (halt ) this active-low bidirectional signal can be asserted with reset to cause a cold reset as above. if asserted alone, it causes the processor to stop after completion of the current bus cycle. as long as halt is held asserted, all bus control signals go to their inactive state, except bgack , and all three-state bus signals (a23?0, d15?0 only) are placed in the high-impedance state. when the processor has stopped executing instructions (e.g., after a double bus fault), the mc68307 asserts this signal. 2.4.4 bus request (br /pa5) this input signal indicates to the mc68307 that an external device desires to become the bus master on the mc68307 external bus. refer to section 3 bus operation for details of the bus arbitration features. when programmed as general-purpose input/output, this signal functions as bit 5 of port a. 2.4.5 bus grant (bg /pa6) this output signal indicates to all external bus master devices (if any) that the mc68307 releases bus control at the end of the current bus cycle to an external requesting bus master. during cold reset, bg reflects the value of br . when programmed as general-purpose input/ output, this signal functions as bit 6 of port a. 2.4.6 bus grant acknowledge (bgack /pa7) this input signal indicates that some other device besides the mc68307 has become the bus master. when programmed as general-purpose input/output, this signal functions as bit 7 of port a. 2.5 clock signals the following paragraphs describe the clock signals. 2.5.1 crystal oscillator (extal, xtal) this input provides two clock generation options (crystal and external clock). extal may be used with xtal to connect an external crystal to the on-chip oscillator and clock gener- ator. if an external clock is used, the clock source should be connected to extal, and xtal must be left unconnected. the oscillator uses an internal frequency equal to the external crystal frequency. the frequency of extal may range from dc to 16.67 mhz, although if a
signal description motorola mc68307 user? manual 2-11 crystal is used it should be in the range 1 mhz to 16.67 mhz. when an external clock is used, it must provide a cmos level at the required system clock frequency. 2.5.2 clock output (clkout) this output clock signal is derived from the on-chip clock oscillator. this clock is used by the processor and the internal peripherals. all mc68307 bus timings are referenced to the clk- out signal rather than the extal input signal, as there is a skew between the two. the clock output is active from reset, but can be turned off by the software writing to the system control register, in order to save power or control external devices. 2.6 test signals the following signals are used with the on-board test logic defined by the ieee 1149.1 stan- dard. refer to section 9 ieee 1149.1 test access port for more information on the use of these signals. 2.6.1 test clock (tck) this input provides a clock for on-board test logic defined by the ieee1149.1 standard. 2.6.2 test mode select (tms) this input controls test mode operations for on-board test logic defined by the ieee 1149.1 standard. connecting tms to v cc disables the test controller, making all jtag circuits transparent to the system. 2.6.3 test data in (tdi) this input is used for serial test instructions and test data for on-board test logic defined by the ieee 1149.1 standard. 2.6.4 test data out (tdo) this output is used for serial test instructions and test data for on-chip test logic defined by the ieee 1149.1 standard. 2.7 m-bus i/o signals the m-bus is an i 2 c-bus-compatible serial interface on two wires. all devices connected to the bus must have open-drain or open-collector outputs. the logical and function is exer- cised on both lines with pullup resistors being required. the pins are multiplexed with port b, individual pin function being programmable. port b bits 0 and 1 are therefore always open-drain input/outputs. refer to section 7 m-bus interface module for more information on these signals. 2.7.1 serial clock (scl/pb0) this bidirectional open-drain signal is the clock signal for the m-bus interface. either it is driven by the m-bus module when the bus is in the master mode or it becomes the clock input when the m-bus is in the slave mode. when programmed as general-purpose input/ output, this signal functions as bit 0 of port b.
signal description 2-12 mc68307 user? manual motorola 2.7.2 serial data (sda/pb1) this bidirectional open-drain signal is the data input/output for the m-bus interface. when programmed as general-purpose input/output, this signal functions as bit 1 of port b. 2.8 uart i/o signals the following signals are used by the uart serial i/o module for data and clock signals. refer to section 8 serial module for more information on these signals. 2.8.1 transmit data (txd/pb2) this bidirectional signal can be programmed as the transmitter serial data output for the uart module. the output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. data is shifted out on this signal at the falling edge of the serial clock source, with the least significant bit transmitted first. when pro- grammed as a general-purpose input/output, this signal functions as bit 2 of the 16-bit sec- ondary port, port b. 2.8.2 receive data (rxd/pb3) this bidirectional signal can be programmed as the receiver serial data input for the uart module. data received on this signal is sampled on the rising edge of the serial clock source, with the least significant bit received first. when the uart clock has been stopped for power-down mode, any transition on this pin can optionally restart it. when programmed as a general-purpose input/output, this signal functions as bit 3 of port b. 2.8.3 request-to-send (rts /pb4) this bidirectional signal can be programmed as an active-low request-to-send output from the uart module. when programmed as a general-purpose input/output, this signal func- tions as bit 4 of port b. 2.8.4 clear-to-send (cts /pb5) this bidirectional input signal can be programmed as the active-low clear-to-send input for the uart module. when programmed as general-purpose input/output, this signal func- tions as bit 5 of port b. 2.9 timer i/o signals the following external signals are used by the timer module. refer to section 6 dual timer module for additional information on these signals. 2.9.1 timer 1 input (tin1/pb6) this bidirectional signal can be programmed as a clock input that causes events to occur in timer/counter channel 1, either causing a clock to the event counter or providing a trigger to the timer value capture logic. when programmed as a general-purpose input/output, this signal functions as bit 6 of port b.
signal description motorola mc68307 user? manual 2-13 2.9.2 timer 2 input (tin2/pb7) this bidirectional signal can be programmed as a clock input that causes events to occur in timer/counter channel 2, either causing a clock to the event counter or providing a trigger to the timer value capture logic. when programmed as general-purpose input/output, this sig- nal functions as bit 7 of port b. 2.9.3 timer 1 output (tout1 /pa3) this bidirectional signal can be programmed to toggle or pulse low for one system clock duration when timer/counter channel 1 reaches a reference value. when programmed as general-purpose i/o, this signal functions as bit 3 of port a. 2.9.4 timer 2 output (tout2 /pa4) this bidirectional signal can be programmed to toggle or pulse low for one system clock duration when timer/counter channel 2 reaches a reference value. when programmed as general-purpose i/o, this signal functions as bit 4 of port a. 2.10 interrupt request inputs these pins can be programmed to be either prioritized interrupt request lines or port b gen- eral-purpose input/output lines. 2.10.1 interrupt inputs (int1 ?nt8 /pb8?b15) these eight bidirectional signals may be configured as general-purpose parallel i/o ports with interrupt capability. each of the pins can be configured either as an input or an output. when configured as an input, each pin can generate a separate, maskable interrupt on a high-to-low transition, which is latched internally. the interrupt request level (ipl) can be programmed individually for each pin, and each causes a unique vector to be fetched during the subsequent interrupt processing. 2.10.2 non-maskable interrupt input (irq7 ) irq7 is the highest priority interrupt available to the ec000 core, it is a nonmaskable inter- rupt (ipl=7) and cannot be superseded by any other interrupt request. this is an active-low input. 2.11 use of pullup resistors in general, pins that are input-only or output-only do not require external pullup resistors. however, see the notes on low power consumption in the following paragraphs. the open-drain bidirectional signals (halt , reset , dtack , scl/pb0, sda/pb1) always require pullup resistors. the bus control outputs (as , uds , lds , r/w ) three-state at reset during bus arbitration and low-power sleep mode. they need pullups only if they are decoded for use in the user? design or if minimum power consumption is required, otherwise they can be left as unconnected outputs.
signal description 2-14 mc68307 user? manual motorola the address and data bus also three-state at reset and during bus arbitration and power- down mode. in this case the designer must decide whether a short period of floating values on the bus is a concern. the internal pullups on the bidirectional data bus pins are not sufficient to drive external levels. again, adding pullups will help minimize power consumption in low-power sleep mode. bidirectional i/o pins default to inputs on reset. if they are to be used as outputs later, or their function changed to an alternate output function for the pin then a pullup or pulldown may be required. one example is the cs2b , cs2c , and cs2d signals, multiplexed with port a lines. if these chip-selects are used they should have pullups otherwise they will float from reset until they are setup. the rstin input can either be left floating or pulled up if the default power-on reset time is required, or can have an external rc network to stretch reset time. refer to section 3.5 reset operation and section 10.1 mc68307 minimum stand-alone system hardware for details of use of this pin. for maximum reliability, unused inputs should not be left floating. if they are input-only, they may be pulled to v cc or ground. unused outputs may be left unconnected. unused i/o pins may be configured as outputs after reset, and left unconnected. if the mc68307 is to be held in reset for extended periods of time in an application (other than what occurs in normal power-on reset or board test sequences) due to a special appli- cation requirement (such as v cc dropping below required specifications, etc.) then three- stated signals and inputs should be pulled up or down. this decreases stress on the device transistors and saves power. refer to section 2.4.1 reset (reset) and section 3.5 reset operation for the condition of all pins during reset. refer to section 12 ordering information and mechanical data for details of pin assign- ments. 2.12 signal index table 2-11 lists the signal index. table 2-11. signal index pin name description of pin function(s) direction tdo test data out output tdi test data in input tms test mode select input tck test clock in input d15?0 data bus bidirectional a23?8 address bus out output a7?0/ad7?d0 address bus out/multiplexed 8051 address/data bidirectional as address strobe output uds upper data strobe output lds lower data strobe output r/w read/write output
signal description motorola mc68307 user? manual 2-15 dtack data acknowledge bidirectional halt system halt bidirectional reset system reset bidirectional rstin power-on reset input cs0 chip select 0 (rom) output cs1 chip select 1 (ram) output cs2 /cs2a chip select 2 (peripherals) output cs3 chip select 3 (8051) output ale 8051-address latch enable output rd 8051-bus read output wr 8051-bus write output extal external clock/crystal in input xtal external crystal output clkout clock to system output busw0 initial data bus width for cs0 input cs2b /pa0 chip select 2b/i/o port a bit 0 bidirectional cs2c /pa1 chip select 2c/i/o port a bit 1 bidirectional cs2d /pa2 chip select 2d/i/o port a bit 2 bidirectional tout1 /pa3 timer 1 output/i/o port a bit 3 bidirectional tout2 /pa4 timer 2 output/i/o port a bit 4 bidirectional br /pa5 bus request input/i/o port a bit 5 bidirectional bg /pa6 bus grant output/i/o port a bit 6 bidirectional bgack /pa7 bus grant acknowledge output/i/o port a bit 7 bidirectional irq7 interrupt level 7 input scl/pb0 serial m-bus clock/port b bit 0 bidirectional sda/pb1 serial m-bus data/port b bit 1 bidirectional txd/pb2 uart transmit data/port b bit 2 bidirectional rxd/pb3 uart receive data/port b bit 3 bidirectional rts /pb4 request-to-send/port b bit 4 bidirectional cts /pb5 clear-to-send/port b bit 5 bidirectional tin1/pb6 timer 1 input/port b bit 6 bidirectional tin2/pb7 timer 2 input/port b bit 7 bidirectional int1 /pb8 interrupt in 1/port b bit 8 bidirectional int2 /pb9 interrupt in 2/port b bit 9 bidirectional int3 /pb10 interrupt in 3/port b bit 10 bidirectional int4 /pb11 interrupt in 4/port b bit 11 bidirectional int5 /pb12 interrupt in 5/port b bit 12 bidirectional int6 /pb13 interrupt in 6/port b bit 13 bidirectional int7 /pb14 interrupt in 7/port b bit 14 bidirectional int8 /pb15 interrupt in 8/port b bit 15 bidirectional table 2-11. signal index (continued) pin name description of pin function(s) direction
motorola mc68307 user? manual 3-1 section 3 bus operation this section describes control signal and bus operation during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. note the terms assertion and negation are used extensively in this manual to avoid confusion when describing a mixture of ?ctive- low?and ?ctive-high?signals. the term assert or assertion is used to indicate that a signal is active or true, independently of whether that level is represented by a high or low voltage. the term negate or negation is used to indicate that a signal is inac- tive or false. 3.1 data transfer operations transfer of data between devices involves the following signals: 1. a23?0 2. d7?0 and/or d15?0 3. control signals the address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure. in all cases, the bus master must deskew all signals it issues at both the start and end of a bus cycle. in addition, the bus master must deskew the acknowledge and data signals from the slave device. the 8051-compatible bus uses a23?0 for both address and data. 3.1.1 16-bit m68000 bus operation the m68000 16-bit bus mode of operation is the default mode of the mc68307. the internal data bus width is 16-bits, and the ec000 core always operates in a 16-bit mode. this mode is appropriate for: external 16-bit memory and peripheral devices, which read and write from the whole data bus, or 8-bit peripherals which do not require a contiguous address space, that is, they occupy either even byte locations only (if connected to the upper half of the data bus) or odd byte locations only (if connecetd to the lower half of the data bus). thi d t t d ith f m k 4 0 4
bus operation 3-2 mc68307 user? manual motorola in this mode address bus a23?1 is used, with data bus d15?0 and control signals as , uds , lds , r/w , and dtack . 3.1.2 16-bit m68000 bus read cycle during a read cycle, the processor receives either one or two bytes of data from the memory or from a peripheral device. if the instruction specifies a word or long-word operation, the processor reads both upper and lower bytes simultaneously by asserting both upper and lower data strobes. a long-word read is accomplished by two consecutive word reads. when the instruction specifies byte operation, the processor uses the internal a0 bit to determine which byte to read and issues the appropriate data strobe. when a0 is zero, the upper data strobe is issued; when a0 is one, the lower data strobe is issued. when the data is received, the processor internally positions the byte appropriately. the word read cycle flowchart is shown in figure 3-1. the byte read cycle flowchart is shown in figure 3-2. the read and write cycle timing is shown in figure 3-3. figure 3-4 shows the word and byte read cycle timing diagram. figure 3-1. word read cycle flowchart (16-bit bus) bus master slave acquire the data input the data start next cycle 1) set r/w to read 2) place address on a23?1 3) assert address strobe (as ) 4) assert upper data strobe (uds ) and lower data strobe (lds ) terminate the cycle address the device 1) latch data 2) negate u ds and l ds 3) negate as 1) decode address 2) place data on d15?0 3) assert data transfer acknowledge (dtack ) 1) remove data from d15?0 2) negate dtack
bus operation motorola mc68307 user? manual 3-3 figure 3-2. byte read cycle flowchart (16-bit bus) figure 3-3. read and write cycle timing diagram (16-bit bus) bus master slave acquire the data input the data start next cycle 1) set r/w to read 2) place address on a23?1 3) assert address strobe (as ) 4) assert upper data strobe (uds ) or lower data strobe (lds ) (based on a0) terminate the cycle address the device 1) latch data 2) negate u ds and l ds 3) negate as 1) decode address 2) place data on d7?0 or d15?8 (based on uds or lds ) 3) assert data transfer acknowledge (dtack ) 1) remove data from d7?0 or d15?8 2) negate dtack s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 w w w w s5 s6 s7 clk a23?0 as uds lds r/w dtack d15?8 d7?0 read write 2 wait state read
bus operation 3-4 mc68307 user? manual motorola a bus cycle consists of eight states. the various signals are asserted during specific states of a read cycle as follows: state 0 the read cycle starts in state 0 (s0). the processor places a valid address on the bus, and drives r/w high to identify a read cycle. state 1 during state 1 (s1), no bus signals are altered. state 2 on the rising edge of state 2 (s2), the processor asserts as and uds /lds . state 3 during state 3 (s3), no bus signals are altered. state 4 during state 4 (s4), the processor waits for a cycle termination signal (dtack or berr ). if neither termination signal is asserted before the falling edge at the end of s4, the processor inserts wait states (full clock cycles) until either dtack or berr is asserted. note that the berr signal does not appear on an external pin on the mc68307; the internal hardware watchdog generates it. case 1: dtack received, with or without berr . state 5 during state 5 (s5), no bus signals are altered. state 6 sometime between state 2 (s2) and state 6 (s6), data from the device is driven onto the data bus. figure 3-4. word and byte read cycle timing diagram (16-bit bus) s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 clk a23?1 as uds lds r/w dtack d15?8 d7?0 word odd byte read even byte read a0
bus operation motorola mc68307 user? manual 3-5 state 7 on the falling edge of the clock entering state 7 (s7), the processor latches data from the addressed device and negates as and uds , lds . the device negates dtack at this time. case 2: berr received without dtack . state 5 during state 5 (s5), no bus signals are altered. state 6 during state 6 (s6), no bus signals are altered. state 7 during state 7 (s7), no bus signals are altered. state 8 during state 8 (s8), no bus signals are altered. state 9 as and uds /lds negated. slave negates berr . 3.1.3 16-bit m68000 bus write cycle during a write cycle, the processor sends bytes of data to the memory or peripheral device. if the instruction specifies a word or long-word operation, the processor issues both uds and lds and writes both bytes. a long-word write is accomplished by two consecutive word writes. when the instruction specifies a byte operation, the processor uses the internal a0 bit to determine which byte to write and issues the appropriate data strobe. when the a0 bit equals zero, uds is asserted; when the a0 bit equals one, lds is asserted. the word write cycle flowchart is shown in figure 3-5. the byte write cycle flowchart is shown in figure 3- 1. the word and byte write cycle timing is shown in figure 3-7. figure 3-5. word write cycle flowchart (16-bit bus) bus master slave terminate output transfer input the data start next cycle 1) place address on a23?1 2) assert address strobe (as ) 3) set r/w to write 4) placr data on d15?0 5) assert upper data strobe (uds ) and lower data strobe (lds ) terminate the cycle address the device 1) negate u ds and l ds 3) negate as 3) remove data from d15?0 4) set r/w to read 1) decode address 2) latch data on d15?0 3) assert data transfer acknowledge (dtack ) 1) negate dtack
bus operation 3-6 mc68307 user? manual motorola figure 3-6. byte write cycle flowchart (16-bit bus) figure 3-7. word and byte write cycle timing diagram bus master slave terminate output transfer input the data start next cycle 1) place address on a23?1 2) assert address strobe (as ) 3) set r/w to write 4) place data on d7?0 or d15?8 (according to internal a0) 5) assert upper data strobe (uds ) or lower data strobe (lds ) (based on internal a0) terminate the cycle address the device 1) negate u ds and l ds 2) negate as 3) remove data from d7?0 or d15?8 4) set r/w to read 1) decode address 2) latch data on d7?0 if lds is asserted. latch data on d15?8 if uds is asserted 3) assert data transfer acknowledge (dtack ) 1) negate dtack s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 a0 clk a23?1 as uds lds r/w dtack d15?8 d7?0 even byte write word write odd byte write
bus operation motorola mc68307 user? manual 3-7 the descriptions of the eight states of a write cycle are as follows: state 0 the write cycle starts in s0. the processor places a valid address on the address bus, and drives r/w high (if a preceding write cycle has left r/w low). state 1 during s1, no bus signals are altered. state 2 on the rising edge of s2, the processor asserts as and drives r/w low. state 3 during s3, the data bus is driven out of the high-impedance state as the data to be written is placed on the bus. state 4 at the rising edge of s4, the processor asserts uds and/or lds ;. the processor waits for a cycle termination signal (dtack or berr ). if neither termination signal is asserted before the falling edge at the end of s4, the processor inserts wait states (full clock cycles) until either dtack or berr is asserted. note that the berr signal does not appear on an external pin on the mc68307; the internal hardware watchdog generates it. case 1: dtack received, with or without berr . state 5 during s5, no bus signals are altered. state 6 during s6, no bus signals are altered. state 7 on the falling edge of the clock entering s7, the processor negates as , uds , and/or lds . as the clock rises at the end of s7, the processor places the data bus in the high-impedance state, and drives r/w high. the device negates dtack or berr at this time. case 2: berr received without dtack . state 5 during state 5 (s5), no bus signals are altered. state 6 during state 6 (s6), no bus signals are altered. state 7 during state 7 (s7), no bus signals are altered. state 8 during state 8 (s8), no bus signals are altered. state 9 as and uds /lds negated. slave negates berr . at the end of s9, three- state data and drive r/w high.
bus operation 3-8 mc68307 user? manual motorola 3.1.4 read-modify-write cycle the read-modify-write cycle performs a read operation, modifies the data in the arithmetic logic unit, and writes the data back to the same address. the address strobe (as ) remains asserted throughout the entire cycle, making the cycle indivisible. the test and set (tas) instruction uses this cycle to provide a signaling capability without deadlock between pro- cessors in a multiprocessing environment. the tas instruction (the only instruction that uses the read-modify-write cycle) only operates on bytes. thus, all read-modify-write cycles are byte operations. the read-modify-write flowchart is shown in figure 3-8 and the timing diagram is shown in figure 3-9. the descriptions of the read-modify-write cycle states are as follows: state 0 the read cycle starts in s0. the processor places a valid address on the address bus, and drives r/w high to identify a read cycle. figure 3-8. read-modify-write cycle flowchart bus master slave start output transfer input the data start next cycle 1) set r/w to read 2) place address on a23?1 3) assert address strobe (as ) 4) assert upper data strobe (uds ) or lower data strobe (lds ) terminate the cycle address the device 1) set r/w to write 2) place data on d7?0 or d15?8 3) assert upper data strobe (uds ) or lower data strobe (lds ) 1) decode address 2) place data on d7?0 or d15?8 3) assert data transfer acknowledge (dtack ) 1) remove data from d7?0 or d15?8 2) negate dtack acquire the data 1) latch data 2) negate uds and lds 3) start data modification input the data 1) store data on d7?0 or d15?8 2) assert data transfer acknowledge (dtack ) terminate the cycle 1) negate dtack terminate output transfer 1) negate u ds and l ds 2) negate as 3) remove data from d7?0 or d15?8 4) set r/w to read
bus operation motorola mc68307 user? manual 3-9 state 1 during s1, no bus signals are altered. state 2 on the rising edge of s2, the processor asserts as and uds /lds . state 3 during s3, no bus signals are altered. state 4 during s4, the processor waits for a cycle termination signal (dtack or berr ). if neither termination signal is asserted before the falling edge at the end of s4, the processor inserts wait states (full clock cycles) until either dtack or berr is asserted. case r1: dtack only. state 5 during s5, no bus signals are altered. state 6 during s6, data from the device are driven onto the data bus. state 7 on the falling edge of the clock entering s7, the processor accepts data from the device and negates uds /lds . the device negates dtack or berr at this time. state 8?1 the bus signals are unaltered during s8?11, during which the arithmetic logic unit makes appropriate modifications to the data. state 12 the write portion of the cycle starts in s12. the address bus lines, as and r/ w remain unaltered. state 13 during s13, no bus signals are altered. state 14 on the rising edge of s14, the processor drives r/w low. figure 3-9. read-modify-write cycle timing diagram clk a23?0 as s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 indivisible cycle uds or lds r/w dtack d15?8 or d7?0 fc2?c0
bus operation 3-10 mc68307 user? manual motorola state 15 during s15, the data bus is driven out of the high-impedance state as the data to be written are placed on the bus. state 16 at the rising edge of s16, the processor asserts uds /lds . the processor waits for dtack or berr . if neither termination signal is asserted before the falling edge at the close of s16, the processor inserts wait states (full clock cycles) until either dtack or berr is asserted. case w1: dtack with or without berr . state 17 during s17, no bus signals are altered. state 18 during s18, no bus signals are altered. state 19 on the falling edge of the clock entering s19, the processor negates as and uds /lds . as the clock rises at the end of s19, the processor places the data bus in the high-impedance state, and drives r/w high. the device negates dtack or berr at this time. case r2: dtack and berr on read. state 5 during s5, no bus signals are altered. state 6 during s6, no bus signals are altered, and data from the device is ignored. state 7 as and uds /lds are negated. the cycle terminates without the write portion. case r3: berr only on read. state 5 during s5, no bus signals are altered. state 6 during s6, no bus signals are altered. state 7 during s7, no bus signals are altered. state 8 during s8, no bus signals are altered. state 9 as and uds /lds are negated. the cycle terminates without the write portion. case w2: berr only on write. state 17 during s17, no bus signals are altered. state 18 during s18, no bus signals are altered. state 19 during s19, no bus signals are altered. state 20 during s20, no bus signals are altered. state 21 the processor negates as and uds /lds .
bus operation motorola mc68307 user? manual 3-11 3.1.5 cpu space cycle a cpu space cycle, indicated when the internal function codes are all high, is a special pro- cessor cycle. in the ec000 core, cpu space is used only for interrupt acknowledge cycles. figure 3-10 shows the encoding of an interrupt acknowledge cycle. no response is expected or allowed from external devices. on the mc68307 this cycle is an indication of the internal interrupt controller? vector response. as the mc68307 implementation does not provide function code pins to differentiate cpu space cycles (the internal function code signals are all high in this type of cycle), care is required when decoding addresses which may match the above address. no problems will be encountered as long as the chip selects are used as a term in the decoding logic. this will ensure that cpu space cycles are not decoded. the interrupt acknowledge cycle places the level of the interrupt being acknowledged on address bits a3?1 and drives all other address lines high. the interrupt acknowledge cycle reads a vector number when the mc68307 interrupt controller places a vector number on the data bus. the timing diagram for an interrupt acknowledge cycle is shown in figure 3-11. 3.1.6 8-bit m68000 dynamically-sized bus m68000 8-bit bus cycles appear when the mc68307 dynamic bus sizing is enabled. this bus sizing adds cycle-by-cycle control of data bus width to the ec000 core bus, as for the mc68020, but with the difference that the bus width is controlled via the chip selects, rather than external dsack1 and dsack0 inputs. this provides the flexibility of differing bus widths for ram, rom and peripherals, without the pin overhead of the mc68020 solution (dsack1 , dsack0 , siz1 and siz0 ). each of the four programmable chip selects has a default bus width of 8- or 16-bits associ- ated with it. the initial bus width of cs0 is set upon reset by the state of the busw external pin (0 for an 8-bit data bus, 1 for a 16-bit data bus). the bus widths for cs2 , cs3 and cs4 should be programmed during system initialization using the buswx bits in the system configuration register (scr), according to the system design. the default after reset is 16-bits wide. all bus accesses not matched by any of the chip selects or the internal peripheral address ranges require an external dtack input to terminate the cycle. the data bus width of such cycles is 16-bits by default; the ebusw bit in the system configuration register (scr) can be cleared to specify external dtack cycles as 8-bit data bus. figure 3-10. interrupt acknowledge cycle ?address bus 11111111111111111111 interrupt acknowledge level 1 310 23
bus operation 3-12 mc68307 user? manual motorola when using the m68000 8-bit bus, transfer of the data between the mc68307 and other de- vices on the bus involves the following signals: address bus a23?0 data bus d15?0 control signals (as , uds , r/w , dtack ). lds is not used. all m68000 8-bit bus cycles use the upper half of the data bus (d15?8) for reads and writes. note that this differs from the static 8-bit bus provided by the mc68hc001, mc68008 and mc68302, which use the lower half (d7?0). therefore, only uds is asserted during such cycles, never lds . the chip select logic can control the data strobes in this way only because it determines the bus width that is pro- grammed for a particular chip-select before dtack is asserted. figure 3-11. interrupt acknowledge cycle timing diagram clk a23?4 as uds * lds r/w dtack d15?8 d7?0 ipl2?pl0 (internal) stack pcl (ssp) iack cycle (vector number acquisition) stack and vector fetch a3?0 although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. the processor does not recognize anything on data lines d15?8 at this time. last bus cycle of instruction (read or write) s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 * ipl2?pl0 transition ipl2?pl0 sampled ipl2?pl0 valid internally
bus operation motorola mc68307 user? manual 3-13 3.1.7 8051-bus operation the 8051-compatible bus is a multiplexed address/data bus scheme which provides an 8- bit-wide data interface to memories and peripherals. it is typically used for asic devices where pin count minimization is important. individual read and write strobes are provided, along with a latch enable signal which indi- cates that the multiplexed portion of the bus is carrying a valid address which is latched by the memory or peripheral device at the beginning of the cycle. when using the 8051-compatible 8-bit bus, transfer of data between the mc68307 and other devices on the bus involves the following signals: address/data multiplexed bus ad7?d0 optionally higher-order address bus a23?8 or part thereof control signals (cs3 , ale, rd , wr ) if the 8051-compatible interface is enabled, one of the mc68307 programmable chip selects (cs3 ) is used to indicate the address range to be decoded as 8051 accesses. the base address and address mask should be programmed as described in section 5.1.2.3 8051- compatible bus chip select . the device being addressed can decode address lines a8 and higher if an addressing range larger than 256-bytes is required, up to the maximum address range of the mc68307. during 8051-compatible bus cycles, the m68000 strobe outputs are still asserted, indicating the ?nderlying?m68000 bus-cycle, and the d15?0 outputs reflect the internal data-bus value being presented to the ec000 processor core. figure 3-12 and figure 3-13 show examples of 8051-compatible read and write cycle timing diagrams, respecitively.
bus operation 3-14 mc68307 user? manual motorola figure 3-12. 8051-compatible read cycle signals figure 3-13. 8051-compatible write cycle signals ale rd ad7 ?ad0 d15?0 address data out address data xds as clk cs3 a23?8 address ale wr ad7 ?ad0 d15?0 address data out address data xds as clk cs3 a23?8 address
bus operation motorola mc68307 user? manual 3-15 3.2 bus arbitration bus arbitration is a technique used by bus master devices to request, to be granted, and to acknowledge bus mastership. bus arbitration consists of the following: 1. asserting a bus mastership request 2. receiving a grant indicating that the bus is available at the end of the current cycle 3. acknowledging that mastership has been assumed figure 3-14 is a flowchart showing the bus arbitration cycle of the ec000 core. figure 3-16 is a timing diagram of the bus arbitration cycle charted in figure 3-14. this technique allows processing of bus requests during data transfer cycles. there are two ways to arbitrate the bus; three-wire and two-wire bus arbitration. the ec000 core can do either two-wire or three-wire bus arbitration. figure 3-14 and figure 3-16 show figure 3-14. three-wire bus arbitration cycle flowchart processor requesting device request the bus rearbitrate or resume assert bus grant (bg ) acknowledge bus mastership grant bus arbitration assert bus request (br ) 1) external arbitration determines next bus master 2) next bus master waits for current cycle to complete 3) next bus master asserts bus grant acknowledge (bgack ) to become new master 4) bus master negates br terminate arbitration 1) negate bg (and wait for bgack to be negated) 2) if br remains asserted after bgack asserted, re-assert bg operate as bus master perform data transfers (read and write cycles) according to the same rules as the processor uses release bus mastership negate bgack processor operation
bus operation 3-16 mc68307 user? manual motorola three-wire bus arbitration and figure 3-15 and figure 3-17 show two-wire bus arbitration. bgack must be pulled high for two-wire bus arbitration. the timing diagram in figure 3-16 shows that the bus request is negated at the time that an acknowledge is asserted. this type of operation applies to a system consisting of a proces- sor and one other device capable of becoming bus master. in systems having several devices that can be bus masters, bus request lines from these devices can be wire-ored at the processor, and more than one bus request signal could occur. the bus grant signal is negated a few clock cycles after the assertion of the bus grant acknowledge signal. however, if bus requests are pending, the processor reasserts bus grant for another request a few clock cycles after bus grant (for the previous request) is negated. in response to this additional assertion of bus grant, external arbitration circuitry selects the next bus master before the current bus master has completed the bus activity. the timing diagram in figure 3-17 also applies to a system consisting of a processor and one other device capable of becoming bus master. since the two-wire bus arbitration scheme does not use a bus grant acknowledge signal, the external master must continue to assert br until it has completed its bus activity. the processor negates bg when br is negated. figure 3-15. two-wire bus arbitration cycle flowchart processor requesting device request the bus rearbitrate or resume assert bus grant (bg ) operate as bus master grant bus arbitration assert bus request (br ) 1) external arbitration determines next bus master 2) next bus master waits for current cycle to complete acknowledge release of negate bus grant (bg ) release bus mastership negate bus request (br ) processor operation bus mastership
bus operation motorola mc68307 user? manual 3-17 3.2.1 requesting the bus external devices capable of becoming bus masters assert br to request the bus. this signal can be wire-ored (not necessarily constructed from open-collector devices) from any of the devices in the system that can become bus master. the processor, which is at a lower bus priority level than the external devices, relinquishes the bus after it completes the current bus cycle. figure 3-16. three-wire bus arbitration timing diagram figure 3-17. two-wire bus arbitration timing diagram clk a23?0 as lds/ uds r/w dtack d15?0 br bg bgack processor dma device processor dma device clk a23?0 as ds r/w dtack d7?0 processor br bg s0 s6 s2 s4 s0 s2 s4 s6 s0 s2 s4 s6 s0 s2 s4 s6 dma device processor dma device
bus operation 3-18 mc68307 user? manual motorola 3.2.2 receiving the bus grant the processor asserts bg as soon as possible. normally, this process immediately follows internal synchronization, except when the processor has made an internal decision to exe- cute the next bus cycle but has not yet asserted as for that cycle. in this case, bg is delayed until as is asserted to indicate to external devices that a bus cycle is in progress. one such case is during a dynamically sized cycle; bg will not assert until the second half of the cycle. bg can be routed through a daisy-chained network or through a specific priority-encoded network. any method of external arbitration that observes the protocol can be used. 3.2.3 acknowledgment of mastership (three-wire bus arbitration only) upon receiving bg , the requesting device waits until as , dtack , and bgack are negated before asserting bgack . the negation of as indicates that the previous bus master has completed its cycle. (no device is allowed to assume bus mastership while as is asserted.) the negation of bgack indicates that the previous master has released the bus. the nega- tion of dtack indicates that the previous slave has terminated the connection to the previ- ous master. (in some applications, dtack might not be included in this function; general- purpose devices would be connected using as only.) when bgack is asserted, the assert- ing device is bus master until it negates bgack . bgack should not be negated until after the bus cycle(s) is complete. a device relinquishes control of the bus by negating bgack . the br from the granted device should be negated after bgack is asserted. if another bus request is pending, bg is reasserted within a few clocks, as described in section 3.3 bus arbitration control . the processor does not perform any external bus cycles before reas- serting bg .
bus operation motorola mc68307 user? manual 3-19 3.3 bus arbitration control all asynchronous bus arbitration signals to the processor are synchronized before being used internally. as shown in figure 3-18, synchronization requires a maximum of one and a half cycles of the system clock. the input asynchronous signal is sampled on the falling edge of the clock and is valid internally after the next rising edge. bus arbitration control is implemented with a finite state machine (see figure 3-19). in figure 3-19, input signals r and a are the internally synchronized versions of br and bgack . the bg output is shown as g, and the internal three-state control signal is shown as t. if t is true, the address, data, and control buses are placed in the high-impedance state when as is negated. all signals are shown in positive logic (active high), regardless of their true active voltage level. state changes (valid outputs) occur on the next rising edge of the clock after the internal signal is valid. a timing diagram of the bus arbitration sequence during a processor bus cycle is shown in figure 3-20. the bus arbitration timing while the bus is inactive (e.g., the processor is per- forming internal operations for a multiply instruction) is shown in figure 3-21. when a bus request is made after the mpu has begun a bus cycle and before as has been asserted (s0), the special sequence shown in figure 3-22 applies. instead of being asserted on the next rising edge of clock, bg is delayed until the second rising edge following its inter- nal assertion. figure 3-20, figure 3-21, and figure 3-22 apply to processors using three-wire bus arbitra- tion. figure 3-23, figure 3-24, and figure 3-25 apply to processors using two-wire bus arbitration. figure 3-18. external asynchronous signal synchronization clk br (external) br (internal) 47 internal signal valid external signal sampled
bus operation 3-20 mc68307 user? manual motorola figure 3-19. bus arbitration unit state diagrams r = bus request internal a = bus grant acknowledge internal g = bus grant t = three-state control to bus control logic x = don't care 1. state machine will not change if the bus is s0 or s1. 2. the address bus will be placed in the high-impedance state if t is asserted and as is negated. ra xx ra ra ra xx r + a xa r a rx 1 1 r r r x r x r r (a) three-wire bus arbitration (b) two-wire bus arbitration gt gt gt gt ra ra ra ra xa ra gt ra gt gt gt gt gt gt gt state 1 state 0 state 4 state 2 state 3
bus operation motorola mc68307 user? manual 3-21 figure 3-20. three-wire bus arbitration timing diagram?rocessor active s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 clk bus three-stated bg asserted br valid internal br sampled br asserted bus released from three state and processor starts next bus cycle bgack negated internal bgack sampled bgack negated br bg bgack a23?0 as uds lds r/w dtack d15?0 processor alternate bus master processor
bus operation 3-22 mc68307 user? manual motorola figure 3-21. three-wire bus arbitration timing diagram?us inactive s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 clk bgack negated bg asserted and bus three stated br valid internal br sampled br asserted br bg bgack a23?0 as uds lds r/w dtack d15?0 bus released from three state and processor starts next bus cycle processor processor bus inactive alternate bus master
bus operation motorola mc68307 user? manual 3-23 figure 3-22. three-wire bus arbitration timing diagram?pecial case bus three-stated bg asserted br valid internal br sampled br asserted bus released from three state and processor starts next bus cycle bgack negated internal bgack sampled bgack negated br bg bgack as uds lds r/w dtack d15?0 s0 s2 s4 s6 s0 s2 s4 s6 s0 clk a23?0 processor alternate bus master processor
bus operation 3-24 mc68307 user? manual motorola figure 3-23. two-wire bus arbitration timing diagram?rocessor active s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 clk bus three-stated bg asserted br valid internal br sampled br asserted bus released from three state and processor starts next bus cycle br negated internal br sampled br negated br bg bgack a23?0 as uds lds r/w dtack d15?0 processor alternate bus master processor
bus operation motorola mc68307 user? manual 3-25 figure 3-24. two-wire bus arbitration timing diagram?us inactive s0 s1 s2 s3 s4 s5 s6 s7 s0 s1 s2 s3 s4 clk br negated bg asserted and bus three stated br valid internal br sampled br asserted br bg bgack a23?0 as uds lds r/w dtack d15?0 bus released from three state and processor starts next bus cycle processor processor bus inactive alternate bus master
bus operation 3-26 mc68307 user? manual motorola figure 3-25. two-wire bus arbitration timing diagram?pecial case bus three-stated bg asserted br valid internal br sampled br asserted bus released from three state and processor starts next bus cycle br negated internal br sampled br negated br bg bgack as uds lds r/w dtack d15?0 s0 s2 s4 s6 s0 s2 s4 s6 s0 clk a23?0 processor alternate bus master processor
bus operation motorola mc68307 user? manual 3-27 3.4 bus error and halt operation in a bus architecture that requires a handshake from an external device, such as the asyn- chronous bus used in the m68000 family, the handshake may not always occur. a bus mon- itor is provided to terminate a bus cycle in error when the expected signal is not asserted. different systems and different devices within the same system require different maximum- response times. this internal circuitry asserts the internal ec000 core bus error signal after the appropriate delay following the assertion of address strobe. 3.4.1 bus error operation when the bus error condition is recognized, the current bus cycle is terminated in s7 for a read cycle, a write cycle, or the read portion of a read-modify-write cycle. for the write por- tion of a read-modify-write cycle, the current bus cycle is terminated in s19. after the aborted bus cycle is terminated, the processor enters exception processing for the bus error exception. during the exception processing sequence, the following information is placed on the supervisor stack: 1. status register 2. program counter (two words, which may be up to five words past the instruction being executed) 3. error information the first two items are identical to the information stacked by any other exception. the ec000 core stacks bus error information to help determine and to correct the error. after the processor has placed the required information on the stack, the bus error exception vector is read from vector table entry 2 (offset $08) and placed in the program counter. the processor resumes execution at the address in the vector, which is the first instruction in the bus error handler routine. refer to figure 3-26 for an example bus error timing diagram.
bus operation 3-28 mc68307 user? manual motorola figure 3-26. bus error timing diagram s0 s2 s4 s6 clk a23?0 ww w w s8 as lds/uds r/w dtack d15?0 berr halt initiate bus error detection initiate bus error stacking response failure read (internal)
bus operation motorola mc68307 user? manual 3-29 3.4.2 retrying the bus cycle if the internal bus error signal is asserted during a bus cycle in which halt is asserted by an external device, the ec000 core will initiate a retry operation. figure 3-27 is a timing dia- gram of the retry operation. the ec000 core terminates the bus cycle, then puts the data bus in the high-impedance state. the processor remains in this state until halt is negated. then the processor retries the preceding cycle using the same function codes, address, and data (for a write opera- tion). berr should be negated at least one clock cycle before halt is negated. notes there is no external connection to berr ; hence, users can not normally initiate a retry operation. the internal bus error is as- serted whenever a write protect violation, address decode con- flict, or hardware watchdog timeout occurs (assuming the offending condition is enabled in the scr). to guarantee that the entire read-modify-write cycle runs cor- rectly and that the write portion of the operation is performed without negating the address strobe, the processor does not re- try a read-modify-write cycle. when berr is asserted during a read-modify-write operation, a bus error operation is performed whether or not halt is asserted. figure 3-27. retry bus cycle timing diagram s0 s2 s4 s6 clk a23?1 s8 s0 s2 s4 s6 as lds/uds r/w dtack d15?0 berr (internal) halt 1 clock period 3 read halt retry
bus operation 3-30 mc68307 user? manual motorola 3.4.3 halt operation halt performs a halt/run/single-step operation. when halt is asserted by an external device, the processor halts and remains halted as long as the signal remains asserted, as shown in figure 3-28. while the processor is halted, bus arbitration is performed as usual. note if halt is asserted while a reset instruction is being executed, the cpu is reset. the single-step mode is derived from correctly timed transitions of halt . halt is negated to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the cycle completes. the single-step mode proceeds through a program one bus cycle at a time for debugging purposes. the halt operation and the hardware trace capability allow tracing of either bus cycles or instructions one at a time. these capabilities and a software debug- ging package provide total debugging flexibility. figure 3-28. halt operation timing diagram s0 s2 s4 s6 clk a23?0 s0 s2 s4 s6 as r/w dtack d15?0 halt lds/uds read halt read
bus operation motorola mc68307 user? manual 3-31 3.4.4 double bus fault when a bus error exception occurs, the processor begins exception processing by stacking information on the supervisor stack. if another bus error occurs during exception processing (i.e., before execution of another instruction begins) the processor halts and asserts halt . this is called a double bus fault. only an external reset operation or a software watchdog timeout can restart a processor halted due to a double bus fault. a double bus fault occurs during a reset operation when a bus error occurs while the pro- cessor is reading the vector table (before the first instruction is executed). the reset opera- tion is described in the following paragraphs. 3.5 reset operation reset can be asserted externally for the initial processor reset. subsequently, the signal can be asserted either externally or internally (executing a reset instruction). for proper external reset operation, halt must also be asserted. the reset and halt bidirectional pins represent the standard m68000 method of reset. the mc68307 adds a master reset input (rstin ) which resets the mc68307. rstin gen- erates a reset , causing external devices in the system to be reset; note that halt is not asserted. at initial power-on, the mc68307? power-on reset asserts reset and halt internally until v dd reaches a minimum level. they are then held asserted for 32768 extal clocks, to ensure that the clock source has time to stabilize. subsequent assertions of rstin also incur a 32768 clock hold after the negating edge, which equates to 2ms for a 16.667 mhz system clock. because of this debouncing effect, this input is often used in preference to reset and halt when a reset switch is required. after the processor is reset, it reads the reset vector table entry (address $00000) and loads the contents into the supervisor stack pointer (ssp). next, the processor loads the contents of address $00004 (vector table entry 1) into the program counter. then the processor ini- tializes the interrupt level in the status register to a value of seven. no other register is affected by the reset sequence. figure 3-29 shows the timing of the reset operation.
bus operation 3-32 mc68307 user? manual motorola the active-low reset signal is asserted by the ec000 core when a reset instruction is executed. this signal should reset all external devices and internal peripherals (the ec000 core itself is not affected). the processor drives reset for 124 clock periods. to guarantee a reset of the core during this time, internal logic will stretch any reset or halt assertion to 132 clocks. 3.6 asynchronous operation to achieve clock frequency independence at a system level, the bus can be operated in an asynchronous manner. asynchronous bus operation uses the bus handshake signals to control the transfer of data. the handshake signals are as , uds , lds , dtack , the internal berr , and halt . as indicates the start of the bus cycle, and uds and lds signal valid data for a write cycle. after placing the requested data on the data bus (read cycle) or latch- ing the data (write cycle), the slave device (memory or peripheral) or the internal wait-state generator asserts dtack to terminate the bus cycle. if no device responds or if the access is invalid, internal control logic asserts the internal berr , to abort the cycle. figure 3-31 shows the use of the bus handshake signals in a fully asynchronous read cycle. figure 3- 30 shows a fully asynchronous write cycle. in the asynchronous mode, the accessed device operates independently of the frequency and phase of the system clock. for example, the mc68681 dual universal asynchronous receiver/transmitter (duart) does not require any clock-related information from the bus master during a bus transfer. asynchronous devices are designed to operate correctly with processors at any clock frequency when relevant timing requirements are observed. a device can use a clock at the same frequency as the system clock, but without a defined phase relationship to the system clock. this mode of operation is pseudo-asynchronous; it figure 3-29. power-on reset operation timing diagram t 4 clocks 23 4 5 6 notes: 1. internal start-up time 2. ssp high read in here 3. ssp low read in here 4. pc high read in here 5. pc low read in here 6. first instruction fetched here bus state unknown: all control signals inactive. data bus in read mode: clk + 3 volts v dd reset halt b us signals < t > 32768 clocks 1
bus operation motorola mc68307 user? manual 3-33 increases performance by observing timing parameters related to the system clock fre- quency without being completely synchronous with that clock. a memory array designed to operate with a particular frequency processor but not driven by the processor clock is a com- mon example of a pseudo-asynchronous device. the designer of a fully asynchronous system can make no assumptions about address setup time, which could be used to improve performance. with the system clock frequency known, the slave device can be designed to decode the address bus before recognizing an address strobe. parameter #11 (refer to section 11.7 ac electrical specifications?ead and write cycles (vcc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; ta = tl to th) (see figure 11-3 and figure 11-4) ) specifies the minimum time before address strobe dur- ing which the address is valid. in a pseudo-asynchronous system, timing specifications allow dtack to be asserted for a read cycle before the data from a slave device is valid. the length of time that dtack may precede data is specified as parameter #31. this parameter must be met to ensure the valid- ity of the data latched into the processor. no maximum time is specified from the assertion of as to the assertion of dtack . during this unlimited time, the processor inserts wait cycles in one-clock-period increments until dtack is recognized. figure 3-33 shows the important timing parameters for a pseudo-asynchronous read cycle. during a write cycle, after the processor asserts as but before driving the data bus, the pro- cessor drives r/w low. parameter #55 specifies the minimum time between the transition figure 3-30. fully asynchronous write cycle figure 3-31. fully asynchronous read cycle addr as r/w uds/lds data dtack addr as r/w u ds /lds data dtack as r/w dtack uds/lds data addr addr as r/w u ds /lds data dtack
bus operation 3-34 mc68307 user? manual motorola of r/w and the driving of the data bus, which is effectively the maximum turnoff time for any device driving the data bus. after the processor places valid data on the bus, it asserts the data strobe signal(s). a data setup time, similar to the address setup time previously discussed, can be used to improve performance. parameter #26 is the minimum time a slave device can accept valid data before recognizing a data strobe. the slave device asserts dtack after it accepts the data. parameter #25 is the minimum time after negation of the strobes during which the valid data remains on the address bus. parameter #28 is the maximum time between the negation of the strobes by the processor and the negation of dtack by the slave device. if dtack remains asserted past the time specified by parameter #28, the processor may recognize it as being asserted early in the next bus cycle and may terminate that cycle prematurely. fig- ure 3-33 shows the important timing specifications for a pseudo-asynchronous write cycle. figure 3-32. pseudo-asynchronous read cycle addr as r/w uds/lds data dtack 11 17 a 31 28 29 addr as r/w uds /lds data dtack
bus operation motorola mc68307 user? manual 3-35 figure 3-33. pseudo-asynchronous write cycle addr as r/w uds/lds data dtack 11 55 22 26 28 29 20a c addr as r/w uds /lds data dtack
bus operation 3-36 mc68307 user? manual motorola 3.7 synchronous operation in some systems, external devices use the system clock to generate dtack and other asynchronous input signals. this synchronous operation provides a closely coupled design with maximum performance, appropriate for frequently accessed parts of the system. for example, memory can operate in the synchronous mode, but peripheral devices operate asynchronously. for a synchronous device, the designer uses explicit timing information shown in section 11.7 ac electrical specifications?ead and write cycles (vcc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; ta = tl to th) (see figure 11-3 and figure 11-4) . these specifications define the state of all bus signals relative to a specific state of the processor clock. the standard m68000 bus cycle consists of four clock periods (eight bus cycle states) and, optionally, an integral number of clock cycles inserted as wait states. wait states are inserted as required to allow sufficient response time for the external device. the following state-by-state description of the bus cycle differs from those descriptions in section 3.1.2 16-bit m68000 bus read cycle and section 3.1.3 16-bit m68000 bus write cycle by including information about the important timing parameters that apply in the bus cycle states. state 0 the bus cycle starts in s0, during which the clock is high. at the rising edge of s0, the function code for the access is driven externally. parameter #6a defines the delay from this rising edge until the function codes are valid. also, the r/w signal is driven high; parameter #18 defines the delay from the same rising edge to the transition of r/w . the minimum value for parameter #18 applies to a read cycle preceded by a write cycle; this value is the maximum hold time for a low on r/w beyond the initiation of the read cycle. state 1 entering s1, a low period of the clock, the address of the accessed device is driven externally with an assertion delay defined by parameter #6. state 2 on the rising edge of s2, a high period of the clock, as is asserted. during a read cycle, uds and/or lds is also asserted at this time. parameter #9 defines the assertion delay for these signals. for a write cycle, the r/w signal is driven low with a delay defined by parameter #20. state 3 on the falling edge of the clock entering s3, the data bus is driven out of the high-impedance state with the data being written to the accessed device (in a write cycle). parameter #23 specifies the data assertion delay. in a read cycle, no signal is altered in s3. state 4 entering the high clock period of s4, uds /lds is asserted (during a write cycle) on the rising edge of the clock. as in s2 for a read cycle, parameter #9 defines the assertion delay from the rising edge of s4 for uds /lds . in a read cycle, no signal is altered by the processor during s4. until the falling edge of the clock at the end of s4 (beginning of s5), no response from any external device except reset is acknowledged by the
bus operation 3-37 mc68307 user? manual motorola processor. if dtack is asserted before the falling edge of s4 and satisfies the input setup time defined by parameter #47, the processor enters s5 and the bus cycle continues. if dtack is asserted but without meeting the setup time defined by parameter #47, the processor may recognize the signal and continue the bus cycle; the result is unpredictable. if dtack is not asserted before the next rise of clock, the bus cycle remains in s4, and wait states (complete clock cycles) are inserted until one of the bus cycle terminations is met. dtack is normally generated by the internal wait-state generator. state 5 s5 is a low period of the clock, during which the processor does not alter any signal. state 6 s6 is a high period of the clock, during which data for a read operation is set up relative to the falling edge (entering s7). parameter #27 defines the minimum period by which the data must precede the falling edge. for a write operation, the processor changes no signal during s6. state 7 on the falling edge of the clock entering s7, the processor latches data and negates as and uds /lds during a read cycle. the hold time for these strobes from this falling edge is specified by parameter #12. the hold time for data relative to the negation of as and uds /lds is specified by parameter #29. for a write cycle, only as and uds /lds , are negated; timing parameter #12 also applies. on the rising edge of the clock, at the end of s7 (which may be the start of s0 for the next bus cycle), the processor places the address bus in the high- impedance state. during a write cycle, the processor also places the data bus in the high-impedance state and drives r/w high. external logic circuitry should respond to the negation of the as and uds /lds by negating dtack , if it was asserted externally. parameter #28 is the hold time for dtack . figure 3-34 shows a synchronous read cycle and the important timing parameters that apply. the timing for a synchronous read cycle, including relevant timing parameters, is shown in figure 3-35. a key consideration when designing in a synchronous environment is the timing for the assertion of dtack by an external device. to properly use external inputs, the processor must synchronize these signals to the internal clock. the processor must sample the exter- nal signal, which has no defined phase relationship to the cpu clock, which may be chang- ing at sampling time, and must determine whether to consider the signal high or low during the succeeding clock period. successful synchronization requires that the internal machine receives a valid logic level, whether the input is high, low, or in transition. parameter #47 of section 11.7 ac electrical specifications?ead and write cycles (vcc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; ta = tl to th) (see figure 11-3 and figure 11-4) is the asynchronous input setup time. signals that meet parameter #47 are guaranteed to be recognized at the next falling edge of the system clock. however, signals that do not meet parameter #47 are not guaranteed to be recognized. in addition, if dtack
bus operation 3-38 mc68307 user? manual motorola is recognized on a falling edge, valid data is latched into the processor (during a read cycle) on the next falling edge, provided the data meets the setup time required (parameter #27). when parameter #27 has been met, parameter #31 may be ignored. if dtack is asserted with the required setup time before the falling edge of s4, no wait states are incurred, and the bus cycle runs at its maximum speed of four clock periods. figure 3-34. synchronous read cycle figure 3-35. synchronous write cycle addr uds/lds r/w as clock dtack 6 9 s0 s1 s2 s3 s4 s5 s6 s7 s0 18 47 27 data addr as uds /lds r/w data dtack clock addr uds/lds r/w as clock dtack 6 s0 s1 s2 s3 s4 s5 s6 s7 s0 18 data 23 53 47 9 addr as uds /lds r/w data dtack clock
motorola mc68307 user? manual 4-1 section 4 ec000 core processor the ec000 core has a 16-bit data bus and 32-bit address bus while the full architecture pro- vides for 32-bit address and data register operations. 4.1 features the following resources are available to the ec000 core: eight 32-bit address registers eight 32-bit data registers 56 powerful instructions operations on five main data types memory-mapped input/output (i/o) 14 addressing modes 4.2 processing states the processor is always in one of three states: normal processing, exception processing, or halted. it is in the normal processing state when executing instructions, fetching instructions and operands, and storing instruction results. exception processing is the transition from program processing to system, interrupt, and exception handling. exception processing includes fetching the exception vector, stacking operations, and refilling the instruction pipe after an exception. the processor enters excep- tion processing when an exceptional internal condition arises such as tracing an instruction, an instruction results in a trap, or executing specific instructions. external conditions, such as interrupts and access errors, also cause exceptions. exception processing ends when the first instruction of the exception handler begins to execute. the processor halts when it receives an access error or generates an address error while in the exception processing state. for example, if during exception processing of one access error another access error occurs, the processor is unable to complete the transition to nor- mal processing and cannot save the internal state of the machine. the processor assumes that the system is not operational and halts. only an external reset can restart a halted pro- cessor. note that when the processor executes a stop instruction, it is in a special type of normal processing state, one without bus cycles. the processor stops, but it does not halt. thi d t t d ith f m k 4 0 4
ec000 core processor 4-2 mc68307 user? manual motorola 4.3 programming model the ec000 core executes instructions in one of two modes?ser mode or supervisor mode. the user mode provides the execution environment for the majority of application programs. the supervisor mode, which allows some additional instructions and privileges, is used by the operating system and other system software. to provide upward compatibility of code written for a specific implementation of the ec000 core, the user programmer's model, illustrated in figure 4-1, is common to all implementa- tions. in the user programmer's model, the ec000 core offers 16, 32-bit, general-purpose registers (d7?0, a7?0), a 32-bit program counter, and an 8-bit condition code register. the first eight registers (d7?0) are used as data registers for byte (8-bit), word (16-bit), and long-word (32-bit) operations. the second set of seven registers (a6?0) and the user stack pointer (usp) can be used as software stack pointers and base address registers. in addi- tion, the address registers can be used for word and long-word operations. all of the 16 reg- isters can be used as index registers. the supervisor programmer's model consists of supplementary registers used in the supervisor mode. the status register, illustrated in figure 4-2, contains the interrupt mask (eight levels avail- able) and the following condition codes: overflow (v), zero (z), negative (n), carry (c), and extend (x). additional status bits indicate that the processor is in the trace (t) mode and/or in the supervisor (s) state. figure 4-1. programming model supervisor programming model user programming model ccr pc a7/usp a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 31 0 31 0 ssp sr (ccr) program counter condition code register supervisor stack pointer status register (ccr is also shown in the user programming model) user stack pointer data registers address registers
ec000 core processor motorola mc68307 user? manual 4-3 4.3.1 data format summary the processor supports the basic data formats of the m68000 family. the instruction set supports operations on other data formats such as memory addresses. the operand data formats supported by the integer unit (iu) are the standard twos- complement data formats defined in the m68000 family architecture. registers, memory, or instructions themselves can contain iu operands. the operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. table 4-1 lists the data formats for the processor. refer to m68000pm/ad, m68000 family programmer? reference manual, for details on data format organization in registers and memory. 4.3.2 addressing capabilities summary the ec000 core supports the basic addressing modes of the m68000 family. the register indirect addressing modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated applica- tions and high-level languages. the program counter indirect mode also has indexing and offset capabilities. this addressing mode is typically required to support position-indepen- dent software. besides these addressing modes, the processor provides index sizing and scaling features. figure 4-2. status register table 4-1. processor data formats operand data format size notes bit 1 bit binary-coded decimal (bcd) 8 bits packed: 2 digits/byte; unpacked: 1 digit/byte byte integer 8 bits word integer 16 bits long-word integer 32 bits t0 s0 0i2i1i0 xnzvc 000 system byte user byte (condition code register) trace mode interrupt priority mask supervisor/user state extend negative zero overflow carry 15 14 13 12 11 10 9 8 7 5 6 43210
ec000 core processor 4-4 mc68307 user? manual motorola an instruction? addressing mode can specify the value of an operand, a register containing the operand, or how to derive the effective address of an operand in memory. each address- ing mode has an assembler syntax. some instructions imply the addressing mode for an operand. these instructions include the appropriate fields for operands that use only one addressing mode. table 4-2 lists a summary of the effective addressing modes for the pro- cessor. refer to m68000pm/ad, m68000 family programmer? reference manual, for details on instruction format and addressing modes. 4.3.3 notation conventions table 4-3 lists the notation conventions used in this manual unless otherwise specified. table 4-2. effective addressing modes addressing modes syntax register direct addressing data register direct address register direct ea = dn ea = an absolute data addressing absolute short absolute long ea = (next word) ea = (next two words) program counter relative addressing relative with offset relative with index and offset ea = (pc)+d 16 ea = (pc)+d 8 register indirect addressing register indirect postincrement register indirect predecrement register indirect register indirect with offset indexed register indirect with offset ea = (an) ea = (an), an an+n an an?, ea = (an) ea = (an)+d 16 ea = (an)+(xn)+d 8 immediate data addressing immediate quick immediate data = next word(s) inherent data implied addressing implied register ea = sr, usp, ssp, pc table 4-3. notation conventions single and double operand operations + arithmetic addition or postincrement indicator. arithmetic subtraction or predecrement indicator. arithmetic multiplication. arithmetic division or conjunction symbol. ~ invert; operand is logically complemented. l logical and v logical or logical exclusive or source operand is moved to destination operand. two operands are exchanged. any double-operand operation. tested operand is compared to zero and the condition codes are set appropriately. sign-extended all bits of the upper portion are made equal to the high-order bit of the lower portion. other operations trap equivalent to format offset word (ssp); ssp ?2 ssp; pc (ssp); ssp ?4 ssp; sr (ssp); ssp ?2 ssp; (vector) pc stop enter the stopped state, waiting for interrupts. 10 the operand is bcd; operations are performed in decimal.
ec000 core processor motorola mc68307 user? manual 4-5 if then else test the condition. if true, the operations after ?hen?are performed. if the condition is false and the optional ?lse?clause is present, the operations after ?lse?are performed. if the condition is false and else is omitted, the instruction performs no operation. refer to the bcc instruction de- scription as an example. register specification an any address register n (example: a3 is address register 3) ax, ay source and destination address registers, respectively. br base register?n, pc, or suppressed. dc data register d7?0, used during compare. dh, dl data registers high- or low-order 32 bits of product. dn any data register n (example: d5 is data register 5) dr, dq data register? remainder or quotient of divide. du data register d7?0, used during update. dx, dy source and destination data registers, respectively. rn any address or data register rx, ry any source and destination registers, respectively. xn index register?n, dn, or suppressed. data format and type operand data format: byte (b), word (w), long (l), or packed (p). b, w, l specifies a signed integer data type (twos complement) of byte, word, or long word. k a twos complement signed integer (?4 to +17) specifying a number? format to be stored in the packed decimal format. subfields and qualifiers # or # immediate data following the instruction word(s). ( ) identifies an indirect address in a register. [ ] identifies an indirect address in memory. bd base displacement d n displacement value, n bits wide (example: d 16 is a 16-bit displacement). lsb least significant bit lsw least significant word msb most significant bit msw most significant word od outer displacement scale a scale factor (1, 2, 4, or 8, for no-word, word, long-word, or quad-word scaling, respectively). size the index register? size (w for word, l for long word). {offset:width} bit field selection. register names ccr condition code register (lower byte of status register) pc program counter sr status register register codes * general case. c carry bit in ccr cc condition codes from ccr fc function code n negative bit in ccr u undefined, reserved for motorola use. v overflow bit in ccr x extend bit in ccr z zero bit in ccr not affected or applicable. table 4-3. notation conventions (continued)
ec000 core processor 4-6 mc68307 user? manual motorola 4.4 ec000 core instruction set overview design of the instruction set gives special emphasis to support of structured, high-level lan- guages and to ease of assembly language programming. each instruction, with a few excep- tions, operates on bytes, words, and long words, and most instructions can use any of the 14 addressing modes. over 1000 useful instructions are provided by combining instruction types, data types, and addressing modes. these instructions include signed and unsigned multiply and divide, ?uick?arithmetic operations, bcd arithmetic, and expanded operations (through traps). additionally, the highly symmetric, proprietary microcoded structure of the instruction set provides a sound, flexible base for the future. the ec000 core instruction set is listed in table 4-4. for detailed information on the ec000 core instruction set, refer to m68000pm/ad, m68000 family programmer's reference man- ual . stack pointers sp active stack pointer ssp supervisor stack pointer usp user stack pointer miscellaneous effective address assemble program label list of registers, for example d3?0. lb lower bound m bit m of an operand m? bits m through n of operand ub upper bound table 4-4. ec000 core instruction set summary opcode operation syntax abcd bcd source + bcd destination + x destination abcd dy,dx abcd ?ay),?ax) add source + destination destination add ,dn add dn, adda source + destination destination adda ,an addi immediate data + destination destination addi #, addq immediate data + destination destination addq #, addx source + destination + x destination addx dy,dx addx ?ay),?ax) and source l destination destination and ,dn and dn, andi immediate data l destination destination andi #, andi to ccr source l ccr ccr andi #,ccr andi to sr if supervisor state then source l sr sr else trap andi #,sr asl, asr destination shifted by count destination asd dx,dy 1 asd #,dy 1 asd 1 bcc if condition true then pc + d n pc bcc table 4-3. notation conventions (continued)
ec000 core processor motorola mc68307 user? manual 4-7 bchg ~(bit number of destination) z; ~(bit number of destination) (bit number) of des- tination bchg dn, bchg #, bclr ~(bit number of destination) z; 0 bit number of destination bclr dn, bclr #, bra pc + d n pc bra bset ~(bit number of destination) z; 1 bit number of destination bset dn, bset #, bsr sp ?4 sp; pc (sp); pc + d n pc bsr btst ?bit number of destination) z; btst dn, btst #, chk if dn < 0 or dn > source then trap chk ,dn clr 0 destination clr cmp destination ?source ? cc cmp ,dn cmpa destination ?source cmpa ,an cmpi destination ?immediate data cmpi #, cmpm destination ?source cc cmpm (ay)+,(ax)+ dbcc if condition false then (dn? dn; if dn ? then pc + d n pc) dbcc dn, divs destination source destination divs.w ,dn 32 16 16r:16q divs.l ,dq 32 32 32q divs.l ,dr:dq 64 32 32r:32q divu destination source destination divu.w ,dn 32 16 16r:16q divu.l ,dq 32 32 32q divu.l ,dr:dq 64 32 32r:32q eor source destination destination eor dn, eori immediate data destination destination eori #, eori to ccr source ccr ccr eori #,ccr eori to sr if supervisor state then source sr sr else trap eori #,sr exg rx ? ry exg dx,dy exg ax,ay exg dx,ay exg ay,dx ext destination sign ?extended destination ext.w dn extend byte to word ext.l dn extend word to long word jmp destination address pc jmp jsr sp ?4 sp; pc (sp) destination address pc jsr lea an lea ,an link sp ?4 sp; an (sp) sp an, sp+d sp link an,d n lsl, lsr destination shifted by count destination lsd dx,dy 1 lsd #,dy 1 lsd 1 move source destination move , move from sr if supervisor state then sr destination else trap move sr, move to ccr source ccr move ,ccr move to sr if supervisor state then source sr else trap move ,sr move usp if supervisor state then usp an or an usp else trap move usp,an move an,usp table 4-4. ec000 core instruction set summary (continued)
ec000 core processor 4-8 mc68307 user? manual motorola movea source destination movea ,an movem registers destination source registers movem , 2 movem , 2 movep source destination movep dx,(d n ,ay) movep (d n ,ay),dx moveq immediate data destination moveq #,dn muls source destination destination muls.w ,dn 16 16 32 muls.l ,dl 32 ? 32 32 muls.l ,dh?l 32 ? 32 64 mulu source destination destination mulu.w ,dn 16 ? 16 32 mulu.l ,dl 32 ? 32 32 mulu.l ,dh?l 32 ? 32 64 nbcd 0 ?(destination 10 ) ?x destination nbcd neg 0 ?(destination) destination neg negx 0 ?(destination) ?x destination negx nop none nop not ~ destination destination not or source v destination destination or ,dn or dn, ori immediate data v destination destination ori #, ori to ccr source v ccr ccr ori #,ccr ori to sr if supervisor state then source v sr sr else trap ori #,sr pea sp ?4 sp; (sp) pea reset if supervisor state then assert rsto line else trap reset rol, ror destination rotated by count destination rod rx,dy 1 rod #,dy 1 roxl, roxr destination rotated with x by count destination roxd dx,dy 1 roxd #,dy 1 roxd 1 rte if supervisor state then (sp) sr; sp + 2 sp; (sp) pc; sp + 4 sp; restore state and deallocate stack according to (sp) else trap rte rtr (sp) ccr; sp + 2 sp; (sp) pc; sp + 4 sp rtr rts (sp) pc; sp + 4 sp rts sbcd destination 10 ?source 10 ?x destination sbcd dx,dy sbcd ?ax),?ay) scc if condition true then 1s destination else 0s destination scc stop if supervisor state then immediate data sr; stop else trap stop # sub destination ?source destination sub ,dn sub dn, suba destination ?source destination suba ,an subi destination ?immediate data destination subi #, subq destination ?immediate data destination subq #, subx destination ?source ?x destination subx dx,dy subx ?ax),?ay) swap register 31?6 ? register 15? swap dn table 4-4. ec000 core instruction set summary (continued)
ec000 core processor motorola mc68307 user? manual 4-9 4.5 exception processing this section describes the processing for each type of exception, exception priorities, the return from an exception, and bus fault recovery. this section also describes the formats of the exception stack frames. exception processing is the activity performed by the processor in preparing to execute a special routine for any condition that causes an exception. in particular, exception processing does not include the execution of the routine itself. exception processing is the transition from the normal processing of a program to the processing required for any special internal or external condition that preempts normal processing. external conditions that cause exceptions are interrupts from external devices, bus errors, and resets. internal conditions that cause exceptions are instructions, address errors, and tracing. for example, the trap, trapv, chk, rte, and div instructions can generate exceptions as part of their normal execution. in addition, illegal instructions and privilege violations cause exceptions. exception processing uses an exception vector table and an exception stack frame. exception processing occurs in four functional steps. however, all individual bus cycles associated with exception processing (vector acquisition, stacking, etc.) are not guaranteed to occur in the order in which they are described in this section. figure 4-4 illustrates a gen- eral flowchart for the steps taken by the processor during exception processing. during the first step, the processor makes an internal copy of the status register, s-bit, t- bits, i-bits (sr). then the processor changes to the supervisor mode by setting the s-bit and inhibits tracing of the exception handler by clearing the trace enable (t) bit in the sr. for the reset and interrupt exceptions, the processor also updates the interrupt priority mask in the sr during the second step, the processor determines the vector number for the exception. for interrupts, the processor performs an interrupt acknowledge bus cycle to obtain the vector number. for all other exceptions, internal logic provides the vector number. this vector num- ber is used in the last step to calculate the address of the exception vector. throughout this section, vector numbers are given in decimal notation. the third step is to save the current processor contents for all exceptions other than reset exception, which does not stack information. the processor creates an exception stack frame on the active supervisor stack and fills it with information appropriate for the type of tas destination tested condition codes; 1 bit 7 of destination tas trap ssp ?2 ssp; format offset (ssp); ssp ?4 ssp; pc (ssp); ssp ?2 ssp; sr (ssp); vector address pc trap # trapv if v then trap trapv tst destination tested condition codes tst unlk an sp; (sp) an; sp + 4 sp unlk an notes: 1. d is direction, left or right. 2. list refers to register. table 4-4. ec000 core instruction set summary (continued)
ec000 core processor 4-10 mc68307 user? manual motorola exception. other information can also be stacked, depending on which exception is being processed and the state of the processor prior to the exception. figure 4-3 illustrates the general form of the exception stack frame. the last step initiates execution of the exception handler. the new program counter value is fetched from the exception vector. the processor then resumes instruction execution. the instruction at the address in the exception vector is fetched, and normal instruction decoding and execution is started. figure 4-4 shows a general exception processiong flowchart. figure 4-3. general form of exception stack frame even byte odd byte program counter low program counter high ssp 15 8 70 0 15 status register higher addres s
ec000 core processor motorola mc68307 user? manual 4-11 figure 4-4. general exception processing flowchart exit fetch vector number (double bus fault) execute exception handler exit (double bus fault) (double bus fault) entry save contents to stack frame (see note) otherwise begin instruction execution otherwise bus error bus error bus error or address error otherwise save internal copy of sr s 1 t 0 (see note) note: these blocks vary for reset and interrupt exceptions. ? ?
ec000 core processor 4-12 mc68307 user? manual motorola 4.5.1 exception vectors an exception vector is a memory location from which the processor fetches the address of a routine to handle an exception. each exception type requires a handler routine and a unique vector. all exception vectors are two words in length (see figure 4-5), except for the reset vector, which is four words long. all exception vectors reside in the supervisor data space, except for the reset vector, which is in the supervisor program space. a vector num- ber is an 8-bit number that is multiplied by four to obtain the offset of an exception vector. vector numbers are generated internally or externally, depending on the cause of the excep- tion. for interrupts, during the interrupt acknowledge bus cycle, a peripheral provides an 8- bit vector number (see figure 4-6) to the processor on data bus lines d7?0. the processor forms the vector offset by left-shifting the vector number two bit positions and zero-filling the upper-order bits to obtain a 32-bit long-word vector offset. in the ec000 core this offset is used as the absolute address to obtain the exception vector itself, which is illus- trated in figure 4-6. the actual address on the address bus is truncated to the number of address bits available on the bus of the particular implementation of the m68000 architecture. in the ec000 core, this is 24 address bits. the memory map for exception vectors is shown in table 4-5. the vector table is 512 words long (1024 bytes), starting at address 0 (decimal) and pro- ceeding through address 1023 (decimal). the vector table provides 255 unique vectors, some of which are reserved for trap and other system function vectors. of the 255, 192 are reserved for user interrupt vectors. however, the first 64 entries are not protected, so user interrupt vectors may overlap at the discretion of the systems designer. 4.6 processing of specific exceptions the exceptions are classified according to their sources, and each type is processed differ- ently. the following paragraphs describe in detail the types of exceptions and the processing of each type. the exception vector assignments are listed in table 4-5. figure 4-5. exception vector format figure 4-6. address translated from 8-bit vector number new program counter (high) new program counter (low) a1= 0 a1= 1 word 0 word 1 even byte (a0=0) even byte (a0=1) all zeroes v7 v6 v5 v4 v3 v2 v1 v0 a23 a0 a10 0 0
ec000 core processor motorola mc68307 user? manual 4-13 table 4-5. exception vector assignments vector number address (decimal) address (hex) address space vector assignment 0 0 000 sp reset: initial ssp 3 1 4 004 sp reset: initial pc 3 2 8 008 sd bus error 3 12 00c sd address error 4 16 010 sd illegal instruction 5 20 014 sd zero divide 6 24 018 sd chk instruction 7 28 01c sd trapv instruction 8 32 020 sd privilege violation 9 36 024 sd trace 10 40 028 sd line 1010 emulator 11 44 02c sd line 1111 emulator 12 1 48 030 sd (unassigned, reserved) 13 1 52 034 sd (unassigned, reserved) 14 1 56 038 sd (unassigned, reserved) 15 60 03c sd uninitialized interrupt vector 6 16?3 1 64?2 040?5c sd (unassigned, reserved) 24 96 060 sd spurious interrupt by berr 4 25 100 064 sd (unassigned, reserved) 26 104 068 sd (unassigned, reserved) 27 108 06c sd (unassigned, reserved) 28 112 070 sd (unassigned, reserved) 29 116 074 sd (unassigned, reserved) 30 120 078 sd (unassigned, reserved) 31 124 07c sd (unassigned, reserved) 32?7 128?88 080?bc sd trap instruction vectors 5 48?9 1 192?36 0c0?ee sd (unassigned, reserved) 60?3 1 240?52 0f0?fc sd module base addr & system configuration regs 64?55 256?020 100?fc sd user interrupt vectors notes: 1. in this table, sp = supervisor program space, sd = supervisor data space. 2. vector numbers 12?4, 16?3, and 48?3 are reserved for future enhancements by motorola (with vectors 60?3 being used by the mc68307 sim). no user peripheral devices should be assigned these numbers. 3. unlike the other vectors which only require two words, reset vector (0) requires four words and is located in the supervisor program space. 4. the ec000 core spurious interrupt vector is taken when there is no bus error indication during interrupt processing. this feature is not used by the mc68307. the mc68307 handles this condition separately; it outputs the spurious interrupt vector from the interrupt controller when it cannot provide an interrupt source. 5. trap #n uses vector number 32+n. 6. vector number 15 is never used in the mc68307. the interrupt controller ensures that there is never an uninitialized interrupt.
ec000 core processor 4-14 mc68307 user? manual motorola 4.6.1 reset exception the reset exception corresponds to the highest exception level. the processing of the reset exception is performed for system initiation and recovery from catastrophic failure. any pro- cessing in progress at the time of the reset is aborted and cannot be recovered. the proces- sor is forced into the supervisor state, and the trace state is forced off. the interrupt priority mask is set at level 7. the vector number is internally generated to reference the reset exception vector at location 0 in the supervisor program space. because no assumptions can be made about the validity of register contents, in particular the ssp, neither the pro- gram counter nor the status register are saved. the address in the first two words of the reset exception vector is fetched as the initial ssp, and the address in the last two words of the reset exception vector is fetched as the initial program counter. finally, instruction exe- cution is started at the address in the program counter. the initial program counter should point to the power-up/restart code. the reset instruction does not cause a reset exception; it asserts the reset signal to reset external devices, which allows the software to reset the system to a known state and continue processing with the next instruction. 4.6.2 interrupt exceptions note in the mc68307, all external and internal interrupt requests are controlled by the interrupt controller. the interrupt controller is always the interrupting device to the ec000 core, supplying the appropriate interrupt request level to the ec000 core via the internal ipl2 ?pl0 lines. when the ec000 core performs an interrupt acknowledge, the interrupt controller provides the corresponding vector on the data bus and terminates the access with a dtack . this section considers the interrupt processing from the perspective of the ec000 core. it is worth noting that, from the mc68307? perspective, the ec000 ipl2 ?pl0 lines are internal, and also the ec000 autovectoring is not supported, but is instead handled separately by the interrupt controller. refer to section 5.1.4 interrupt processing for further information on the interrupt operation. seven levels of interrupt priorities are provided, numbered from 1?. level 7 has the highest priority. devices can be chained externally within interrupt priority levels, allowing an unlim- ited number of peripheral devices to interrupt the processor. the status register contains a 3-bit mask indicating the current interrupt priority, and interrupts are inhibited for all priority levels less than or equal to the current priority. priority level 7 is a special case. level 7 inter- rupts cannot be inhibited by the interrupt priority mask, thus providing a non-maskable inter- rupt capability. an interrupt is generated each time the interrupt request level changes from some lower level to level 7. a level 7 interrupt may still be caused by the level comparison if the request level is a 7 and the processor priority is set to a lower level by an instruction.
ec000 core processor motorola mc68307 user? manual 4-15 an interrupt request is made to the processor by encoding the interrupt request level on the ipl2 ?pl0 ; a zero indicates no interrupt request. interrupt requests arriving at the processor do not force immediate exception processing, but the requests are made pending. pending interrupts are detected between instruction executions. if the priority of the pending interrupt is lower than or equal to the current processor priority, execution continues with the next instruction, and the interrupt exception processing is postponed until the priority of the pend- ing interrupt becomes greater than the current processor priority. if the priority of the pending interrupt is greater than the current processor priority, the excep- tion processing sequence is started. a copy of the status register is saved; the privilege mode is set to supervisor mode; tracing is suppressed; and the processor priority level is set to the level of the interrupt being acknowledged. the processor fetches the vector number from the interrupting device by executing an interrupt acknowledge cycle, which displays the level number of the interrupt being acknowledged on the address bus. if external logic requests an automatic vector, the processor internally generates a vector number corre- sponding to the interrupt level number. if external logic indicates a bus error, the interrupt is considered spurious, and the generated vector number references the spurious interrupt vector. the processor then proceeds with the usual exception processing. the saved value of the program counter is the address of the instruction that would have been executed had the interrupt not been taken. the appropriate interrupt vector is fetched and loaded into the program counter, and normal instruction execution commences in the interrupt handling rou- tine. 4.6.3 uninitialized interrupt exception note the uninitialized interrupt vector of the ec000 core is never used in the mc68307, but is described here for completeness; the mc68307 handles all interrupt conditions separately in the interrupt controller (see section 5.1.4 interrupt processing ). an interrupting device provides a ec000 core interrupt vector number and asserts data transfer acknowledge (dtack ) or bus error (berr ) during an interrupt acknowledge cycle by the ec000 core. if the vector register has not been initialized, the responding m68000 family peripheral provides vector number 15, the uninitialized interrupt vector. this response conforms to a uniform way to recover from a programming error. 4.6.4 spurious interrupt exception note the spurious interrupt vector of the ec000 core is never used in the mc68307, but is described here for completeness; the mc68307 handles all interrupt conditions separately in the inter- rupt controller (see section 5.1.4 interrupt processing ). during the interrupt acknowledge cycle, if no device responds by asserting dtack , berr should be asserted to terminate the vector acquisition. the processor separates the pro- cessing of this error from bus error by forming a short format exception stack and fetching
ec000 core processor 4-16 mc68307 user? manual motorola the spurious interrupt vector instead of the bus error vector. the processor then proceeds with the usual exception processing. 4.6.5 instruction traps traps are exceptions caused by instructions; they occur when a processor recognizes an abnormal condition during instruction execution or when an instruction is executed that nor- mally traps during execution. exception processing for traps is straightforward. the status register is copied; the supervi- sor mode is entered; and tracing is turned off. the vector number is internally generated; for the trap instruction, part of the vector number comes from the instruction itself. the pro- gram counter, and the copy of the status register are saved on the supervisor stack. the saved value of the program counter is the address of the instruction following the instruction that generated the trap. finally, instruction execution commences at the address in the exception vector. some instructions are used specifically to generate traps. the trap instruction always forces an exception and is useful for implementing system calls for user programs. the trapv and chk instructions force an exception if the user program detects a run-time error, which may be an arithmetic overflow or a subscript out of bounds. a signed divide (divs) or unsigned divide (divu) instruction forces an exception if a division operation is attempted with a divisor of zero. 4.6.6 illegal and unimplemented instructions illegal instruction is the term used to refer to any of the word bit patterns that do not match the bit pattern of the first word of a legal processor instruction. if such an instruction is fetched, an illegal instruction exception occurs. motorola reserves the right to define instruc- tions using the opcodes of any of the illegal instructions. three bit patterns always force an illegal instruction trap on all m68000 family-compatible microprocessors. the patterns are: $4afa, $4afb, and $4afc. two of the patterns, $4afa and $4afb, are reserved for motorola system products. the third pattern, $4afc, is reserved for customer use (as the take illegal instruction trap (illegal) instruction). word patterns with bits 15?2 equaling 1010 or 1111 are distinguished as unimplemented instructions, and separate exception vectors are assigned to these patterns to permit effi- cient emulation. these separate vectors allow the operating system to emulate unimple- mented instructions in software. exception processing for illegal instructions is similar to that for traps. after the instruction is fetched and decoding is attempted, the processor determines that execution of an illegal instruction is being attempted and starts exception processing. the exception stack frame is then pushed on the supervisor stack, and the illegal instruction vector is fetched.
ec000 core processor motorola mc68307 user? manual 4-17 4.6.7 privilege violations to provide system security, various instructions are privileged. an attempt to execute one of the privileged instructions while in the user mode causes an exception. the privileged in- structions are as follows: and immediate to sr move usp eor immediate to sr or immediate to sr move to sr reset move from sr rte movec stop moves exception processing for privilege violations is nearly identical to that for illegal instructions. after the instruction is fetched and decoded and the processor determines that a privilege violation is being attempted, the processor starts exception processing. the status register is copied; the supervisor mode is entered; and tracing is turned off. the vector number is generated to reference the privilege violation vector, and the current program counter and the copy of the status register are saved on the supervisor stack. the saved value of the program counter is the address of the first word of the instruction causing the privilege vio- lation. finally, instruction execution commences at the address in the privilege violation exception vector. 4.6.8 tracing to aid in program development, the ec000 core includes a facility to allow tracing following each instruction. when tracing is enabled, an exception is forced after each instruction is executed. thus, a debugging program can monitor the execution of the program under test. the trace facility is controlled by the t-bit in the supervisor portion of the status register. if the t-bit is cleared (off), tracing is disabled and instruction execution proceeds from instruc- tion to instruction as normal. if the t-bit is set (on) at the beginning of the execution of an instruction, a trace exception is generated after the instruction is completed. if the instruction is not executed because an interrupt is taken or because the instruction is illegal or privi- leged, the trace exception does not occur. the trace exception also does not occur if the instruction is aborted by a reset, bus error, or address error exception. if the instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception. during the execution of the instruction, if an exception is forced by that instruction, the exception processing for the instruction exception occurs before that of the trace exception. as an extreme illustration of these rules, consider the arrival of an interrupt during the exe- cution of a trap instruction while tracing is enabled. first, the trap exception is processed, then the trace exception, and finally the interrupt exception. instruction execution resumes in the interrupt handler routine. after the execution of the instruction is complete and before the start of the next instruction, exception processing for a trace begins. a copy is made of the status register. the transition to supervisor mode is made, and the t-bit of the status register is turned off, disabling further tracing. the vector number is generated to reference the trace exception vector, and the cur-
ec000 core processor 4-18 mc68307 user? manual motorola rent program counter and the copy of the status register are saved on the supervisor stack. the saved value of the program counter is the address of the next instruction. instruction execution commences at the address contained in the trace exception vector. 4.6.9 bus error when a bus error exception occurs, the current bus cycle is aborted. the current processor activity, whether instruction or exception processing, is terminated, and the processor imme- diately begins exception processing. exception processing for a bus error follows the usual sequence of steps. the status register is copied, the supervisor mode is entered, and tracing is turned off. the vector number is generated to refer to the bus error vector. since the processor is fetching the instruction or an operand when the error occurs, the context of the processor is more detailed. to save more of this context, additional information is saved on the supervisor stack. the program counter and the copy of the status register are saved. the value saved for the program counter is advanced 2?0 bytes beyond the address of the first word of the instruction that made the reference causing the bus error. if the bus error occurred during the fetch of the next instruction, the saved program counter has a value in the vicinity of the current instruc- tion, even if the current instruction is a branch, a jump, or a return instruction. in addition to the usual information, the processor saves its internal copy of the first word of the instruction being processed and the address being accessed by the aborted bus cycle. specific infor- mation about the access is also saved: type of access (read or write), processor activity (pro- cessing an instruction), and function code outputs when the bus error occurred. the processor is processing an instruction if it is in the normal state or processing a group 2 exception; the processor is not processing an instruction if it is processing a group 0 or a group 1 exception. figure 4-7 illustrates how this information is organized on the supervisor stack. if a bus error occurs during the last step of exception processing, while either reading the exception vector or fetching the instruction, the value of the program counter is the address of the exception vector. although this information is not generally sufficient to effect full recovery from the bus error, it does allow software diagnosis. finally, the processor com- mences instruction processing at the address in the vector. it is the responsibility of the error handler routine to clean up the stack and determine where to continue execution. if a bus error occurs during the exception processing for a bus error, an address error, or a reset, the processor halts and all processing ceases. this halt simplifies the detection of a catastrophic system failure, since the processor removes itself from the system to protect memory contents from erroneous accesses. only an external reset operation can restart a halted processor. 4.6.10 address error an address error exception occurs when the processor attempts to access a word or long- word operand or an instruction at an odd address. an address error is similar to an internally generated bus error. the bus cycle is aborted, and the processor ceases current processing and begins exception processing. the exception processing sequence is the same as that for a bus error, including the information to be stacked, except that the vector number refers to the address error vector. likewise, if an address error occurs during the exception pro- cessing for a bus error, address error, or reset, the processor is halted.
ec000 core processor motorola mc68307 user? manual 4-19 4.6.11 multiple exceptions when multiple exceptions occur simultaneously, they are processed according to a fixed pri- ority. table 4-6 lists the exceptions, grouped by characteristics, with group 0 as the highest priority. within group 0, reset has highest priority, followed by address error and then bus error. within group 1, trace has priority over external interrupts, which in turn takes priority over illegal instruction and privilege violation. since only one instruction can be executed at a time, no priority relationship applies within group 2. the priority relationship between two exceptions determines which is taken, or taken first, if the conditions for both arise simultaneously. therefore, if a bus error occurs during a trap instruction, the bus error takes precedence, and the trap instruction processing is aborted. in another example, if an interrupt request occurs during the execution of an instruction while the t-bit in the status register (sr) is asserted, the trace exception has priority and is pro- cessed first. before instruction execution resumes, however, the interrupt exception is also processed, and instruction processing finally commences in the interrupt handler routine. as a general rule, the lower the priority of an exception, the sooner the handler routine for that exception executes. this rule does not apply to the reset exception; its handler is executed first even though it has the highest priority, because the reset operation clears all other exceptions. figure 4-7. supervisor stack order for bus or address error exception table 4-6. exception grouping and priority group exception processing 0 reset, address error, and bus error exception processing begins within two clock cycles. 1 trace, interrupt, illegal, and privilege exception processing begins before the next instruction. 2 trap, trapv, chk, and div exception processing is started by normal instruction execution. lower address 0 15 i/n function code high low 2 3 4 5 r/w status register instruction register low high access address program counter r/w (read/write): write = 0, read = 1. i/n (instruction/not): instruction = 0, not = 1.
motorola mc68307 user? manual 5-1 section 5 system integration module the mc68307 system integration module (sim) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum number of external devices. the sim contains the following functions: system configuration oscillator and clock dividers reset control, power-down mode control chip selects and wait states external bus interfaces, m68000 and 8051-compatible parallel input/output lines with interrupt capability interrupt configuration/response the mc68307 sim is similar to the system integration logic found in other motorola integrated processors, the m68000 family, although each is tailored to the specific needs of the part and its intended application. thi d t t d ith f m k 4 0 4
system integration module 5-2 mc68307 user? manual motorola 5.1 module operation the various internal functional blocks of the sim are described here, with a description of operation of each, along with methods and recommendations for programming the register locations that configure the mc68307 to suit the user's target system. 5.1.1 mc68307 system configuration the mc68307 system configuration logic consists of a module base address register (mbar), and a system control register (scr) which together allow the user to configure op- eration of the following functions: base address and address space of internal peripheral registers low-power (standby) modes hardware watchdog modes for system protection 8051-compatible bus enable or disable peripheral chip selects enable or disable data bus size control for chip selected address ranges 5.1.1.1 module base address register operation. the mbar, must be programmed upon cold reset in order to specify the base address of the various registers which comprise the sim and the other on-chip peripherals. the format of this register is described later in this section, along with a description of the complete memory map of the ec000 internal registers and peripherals. the on-chip peripherals require a reserved 4096-byte block of address space for their registers. this block location is determined by writing the intended base address to the mbar in supervisor data space. the mbar is an on-chip read/write register which is located at an unused vector entry in the mc68307 vector table. the address of the mbar entry within the vector table is $0000f2; it is a 16-bit value. for further details, refer to section 5.2.1 system configuration and protection registers . the module base address and on-chip peripherals address decode logic block diagram is shown here in figure 5-1. after a cold reset, the on-chip peripheral base address is undefined and it is not possible to access the on-chip peripherals at any address until the mbar is written. the mbar and the scr can always be accessed at their fixed addresses. do not assign other devices on the system bus an address that falls within the address range of the on-chip peripherals defined by the mbar. bus contention could result if this is done inadvertently. if this happens, the address decode conflict (adc) status bit in the scr is set. this can cause a berr to be generated, if the address decode conflict enable (adce) bit in the scr is set.
system integration module motorola mc68307 user? manual 5-3 note the mbar and scr registers are internally reset only when a cold reset occurs by the simultaneous assertion of reset and halt , assertion of rstin , power-on reset or software watch- dog timeout. they are unaffected by a wake-up from power- down mode. the chip select (csx ) lines are not asserted on ac- cesses to the mbar and scr locations. thus, it is very conve- nient to use csx lines to select external rom/ram that overlaps or encloses the mbar and scr register locations ($0000f0- $0000ff), since no potential bus contention can occur. if exter- nally-decoded chip selects are used, then contention cannot be ignored. figure 5-1. module base address, decode logic chip-select module registers uart module registers m-bus module registers timer module registers interrupt controller registers input/output port registers module address decode logic ec000 core d15?0 fc2? a23?0 ctrl module base address reg
system integration module 5-4 mc68307 user? manual motorola 5.1.1.2 system control register functions. the scr allows various settings to be made which influence the operation of the system, for example, power-down and oscillator control logic, the bus interface, and the hardware watchdog protection. it also includes status bits which allow exception handler code to monitor the cause of exceptions and resets. most of the functions controlled by these register bits are described in detail elsewhere; they include: cd enable divided frequency to ec000 core lpen low-power enable (to select low-power sleep mode) ckd clock-output disable (to inhibit clkout pin and therefore save power) lpcd2? processor clock speed during low-power modes uacd clock disable for uart peripheral module mbcd clock disable for m-bus peripheral module tmcd clock disable for timer peripheral module uacw auto wakeup of uart clock if data received busw0 chip select 0 bus width 8-bit or 16-bit busw1 chip select 1 bus width 8-bit or 16-bit busw2 chip select 2 bus width 8-bit or 16-bit busw3 chip select 3 bus width 8-bit or 16-bit epcs chip select 2a-2d peripheral chip select mode enable e8051 chip select 3 8051-compatible bus interface enable adce address decode conflict enable to cause berr wpve write protect violation enable to cause berr hwde hardware watchdog enable hw2? hardware watchdog timeout value setting status bits included in the scr are: rs1? reset source register adc address decode conflict status bit wpv write protect violation status bit hwt hardware timeout status bit
system integration module motorola mc68307 user? manual 5-5 5.1.1.3 system protection functions. the facilities provided for system protection are the hardware watchdog (bus monitor) and the software watchdog timer. the hardware watchdog provides a bus monitor which causes an internal bus error (berr assertion) when a bus cycle is not terminated by dtack after a programmable number of clock cycles has elapsed. the hardware watchdog timeout (hwt) status bit in the scr is also set, so that a bus error exception handler can determine the cause of the bus error. the hardware watchdog logic consists of a 10-bit down-counter and a 4-bit fixed prescaler. when enabled, the watchdog timer commences counting clock cycles as as is asserted (for internal or external bus masters). the count is terminated normally by the negation of as ; however, if the count reaches zero before as is negated, berr is asserted until as is negated. the hardware watchdog logic uses four control bits and one status bit in the scr. the effective range of the bus timeout is from 128 clock cycles to 16384 clock cycles (at 16mhz, from 8 m s to 1ms). for operation of the software watchdog timer, refer to section 6 dual timer module . 5.1.2 chip select and wait-state logic the mc68307 provides a set of four programmable chip-select signals. each has a common set of features and some have particular special features associated with them. these features were described in terms of the mc68307 input/output pins in section 2 signal description , but will be described again here in detail. for each memory area the user may also define an internally generated cycle termination signal (dtack ) with programmable number of wait-states. this feature eliminates board space that would otherwise be necessary for cycle termination logic. the four chip selects allow up to four different classes of memory to be used in a system without external decode or wait-state generation logic. for example, a typical configuration could be a 8-bit eprom, a fast 16-bit sram, up to four simple i/o peripherals, and a non- volatile ram with an 8051-compatible interface. the chip select block diagram is shown in figure 5-2. the basic chip select model allows the chip select output signal to assert in response to an address match. the signals are asserted externally shortly after as goes low. the address match is described in terms of a base address and an address mask. thus the size in bytes of the matching block must be a power of 2, and the base address must be an integer multiple of this size. thus an 8-kbyte block size must begin on an 8-kbyte boundary, and a 64-kbyte block size can only begin on a 64-kbyte boundary, etc. the minimum resolution of block size, and hence base address, is any multiple of 8192, because only address lines a23 down to a13 are compared or masked. each chip select can be enabled or disabled independently of the others, and the registers are read-write so that the values programmed can be read back.
system integration module 5-6 mc68307 user? manual motorola for a given chip select block, the user may also choose whether the chip select allows read- only, write-only, or read/write accesses, whether the chip select should match only one function code value or all values, whether a dtack is automatically generated for this chip select and after how many wait states (from zero to six). 5.1.2.1 programmable data-bus size. each of the chip selects include the facility of a data-bus port sizing extension to the basic m68000 bus which allows the system designer to mix 16-bit and 8-bit contiguous address memory devices (ram, rom) on a 16-bit data bus system. if the ec000 core executes a 16-bit data transfer instruction, then two 8-bit bus cycles appear, using the external m68000 data bus upper half (d15?8) only, the least significant bit of address (a0) incrementing automatically from one to the next. a0 should be ignored in 16-bit data-bus cycles, even if only the upper or lower byte is being read/written. note that a 16-bit data bus is always used internally for access to peripheral registers, regardless of any mode settings for the external bus. where peripheral registers are 16-bits wide, they can be read or written in one bus cycle only, eliminating possible conflicts and reading of inaccurate values where 16-bit-wide register contents are volatile (timer counter registers, for example) or where the whole 16-bit value affects some aspect of system operation (chip select base address, for example). where internal peripherals are 8-bits wide, e.g., the mc68681-compatible uart, they are accessed at every alternate (odd) address. it is recommended that any external peripheral that needs only an 8-bit data-bus interface but does not require contiguous address locations, uses a chip select configured as 16-bit data-bus width, and connects to d7?0. this balances more evenly the load on the two halves of the data bus in an 8-bit system. figure 5-2. chip-select block diagram base register 0 (br0) compare logic option register0 (or0) cs0 cs0 cs1 cs2 cs3 dtack generation r/w cs1 cs2 cs3 data bus address and function codes
system integration module motorola mc68307 user? manual 5-7 the default for each chip select is a 16-bit data-bus width. the buswx bits in the scr enable 8-bit data-bus width for each of the four chip select ranges. the initial bus width for chip select 0 is selected by placing a logic 0 or 1 on the busw pin at reset, to specify 8-bit or 16-bit wide data bus respectively. this allows a boot eprom of either data bus width to be used in any given system. all external accesses which do not match one of the chip select address ranges use the value of the ebusw bit in the scr to determine their data bus width. note if byte operations are performed where 8-bit bus mode is used, there is no difference in throughput compared to 16-bit bus mode. however, if 32-bit long word or 16-bit word operations are used over the 8-bit data bus (including all instruction fetches), the performance is exactly half that of the equivalent speed 16- bit-wide data bus. 5.1.2.2 peripheral chip selects. chip select 2 (cs2 signal) features a peripheral chip select (pcs) mode, selected by setting the enable peripheral chip select (epcs) bit in the scr. if this chip select is programmed with a block size of 64 kbytes, and the epcs bit in the scr set, then the cs2 /cs2a pin, along with cs2b , cs2c , and cs2d (which are multiplexed with port a input/output lines) function as four peripheral chip selects, each gated to select a particular 16-kbyte block within the programmed 64-kbyte range. for example, if the base address is programmed as $100000 with size $10000 (64k), and the pcs mode is enabled, then the blocks are selected according to table 5-1: this feature is ideal for miscellaneous peripheral devices in the address space, even if they only require one or two bytes per peripheral. if this feature is not enabled (refer to section 5.2.1.2 system control register (scr) ), then the cs2 /cs2a pin functions as cs2 , a general-purpose programmable m68000-bus chip select, and the cs2b , cs2c and cs2d signals are never asserted. note port a general-purpose i/o lines have programmable control over their function on a bit by bit basis, via the port a control reg- ister (pacnt). for example it is possible to use only cs2a and cs2b , leaving the port a lines which would have been used by cs2c and cs2d , to function as general-purpose i/o. table 5-1. address block selection in peripheral chip select mode chip select pin address block a15 a14 start address end address cs2a $100000 $103fff 0 0 cs2b $104000 $107fff 0 1 cs2c $108000 $10bfff 1 0 cs2d $10c000 $10ffff 1 1
system integration module 5-8 mc68307 user? manual motorola 5.1.2.3 8051-compatible bus chip select. chip select 3 (cs3 signal) can be used to define the addressing range of the 8051-compatible bus mode, when this mode is enabled in the scr e8051 bit. otherwise (if the 8051-compatible bus mode is not used) chip select 3 is available for any general purpose memory or peripheral. in this case, the 8051- compatible bus read and write strobes (rd and wr ), and the address latch enable (ale) signal are always negated. this bus always uses an 8-bit data-bus width, and so the busw3 bit in the scr should be set along with the e8051 bit. 5.1.2.4 global chip select operation (reset defaults). chip select 0 is initialized from cold reset to assert in response to any address in the first 8k bytes of memory space, in order to ensure a chip select to the boot rom or eprom, to fetch the reset vector and execute the initialization code, which should set up the module base address and the four chip select ranges early on in that initialization sequence. the data bus port size for cs0 on reset, and hence the data width of the boot rom device, are programmed by placing logic 0 or 1 on the busw pin during reset, for 8-bit and 16-bit wide data bus respectively. the other 3 chip selects are initialized to be invalid, and so do not assert until they are programmed. 5.1.2.5 overlap in chip select ranges. the user should not normally program more than one chip select line to the same area. if this accidentally occurs, only one chip select line is driven because of internal line priorities. cs0 has the highest priority, and cs3 the lowest. the address compare logic sets the address decode conflict (adc) status bit in the scr, and also generates a bus error (or berr is asserted) if the address decode conflict enable (adce) bit was set by the user in the scr. berr is never asserted on write accesses to the chip select registers. if one chip select is programmed to be read-only, and another is programmed to be write- only, then there is no overlap conflict between these two chip selects, and the address decode conflict (adc) status bit in the scr is not set. when the cpu attempts to write to a read-only location, as programmed by the user when setting up the chip selects, the chip select logic sets the write protect violation (wpv) bit in the scr, and will also generate berr if the write protect violation enable (wpve) bit is set in the scr. the csx line is not asserted. note the chip select logic is reset only on cold reset (assertion of reset and halt , or rstin ). the chip select (csx ) lines are never asserted on accesses to the mbar and scr locations. thus, it is very convenient to use csx lines to select external rom/ram that overlaps or encloses the mbar and scr
system integration module motorola mc68307 user? manual 5-9 register locations ($0000f0?0000ff), since no potential bus contention can occur. the chip select logic does not allow an address match during in- terrupt acknowledge (function code 7) cycles. the programming of the chip select module is discussed in the next chapter. for further information, refer to section 5.2.2 chip select registers . 5.1.3 external bus interface logic this logic controls the interaction of the ec000 core processor, the on-chip m68000 peripheral bus, the external m68000 and 8051-compatible buses, in conjunction with the programmable chip select logic and the various user settings in the system configuration and protection logic. a block diagram of this logic is shown in figure 5-3. 5.1.3.1 m68000 bus interface. the m68000 bus interface adds bus-sizing functionality (8-bit or 16-bit data bus) to the basic m68000 bus of the ec000 core processor. the external bus interface logic links the data bus multiplexers with the programmable chip selects and scr bits, and co-ordinates an 8-bit or 16-bit bus transfer. the buswx bits in the scr define the current data-bus width (port size) for each of the four chip selects. on cold reset, the figure 5-3. external bus interface logic ale wr rd ad7?d0 d15?0 a23?8 cs2 /cs2a cs2 pa0/cs2b pa1/cs2c pa2/cs2d cs3 cs3 cs1 cs0 e8051 epcs port a data port a ddr port a control pax ec000 core d15?0 ctrl a23?0 chip-selects control scr epcs e8051 buswx port a logic padat paddr pacnt port a mux logic periph chip-select decode 8051-bus timing and mux logic external data bus size control logic cs0 cs1 cs2 cs3
system integration module 5-10 mc68307 user? manual motorola default state of busw0 reflects the value of the busw external pin (0 = 8-bit data bus, 1 = 16-bit data bus), and the default state of the other buswx bits is for a 16-bit port size. when the data-bus sizing logic is used to configure a chip select as an 8-bit port select, any 16-bit bus cycles from the processor appears on the external pins as two 8-bit read or write cycles with normal m68000 timings on all signals and the addition of a valid a0 signal. d15 d8 is always used for bus cycles of this kind. note if byte operations are performed where 8-bit bus mode is used, there is no difference in throughput compared to 16-bit bus mode. however, if 32-bit long word or 16-bit word operations are used over the 8-bit data bus (including all instruction fetches), the performance is exactly half that of the equivalent speed 16- bit-wide data bus. 5.1.3.2 8051-compatible bus interface. the 8051-compatible bus interface contains logic to multiplex the low eight address lines (a7?0) and the low eight data lines (d7?0) onto the same pins. cs3 is used to select the memory area assigned to the 8051- compatible bus, it controls the external bus interface logic, triggering the address latch enable signal, and gating the rd and wr signals. refer to section 5.1.2 chip select and wait-state logic and section 5.2.2 chip select registers for details of how to configure the chip select logic for this interface. also refer to section 5.2.1 system configuration and protection registers for details of how to configure the mc68307 pins for the 8051- compatible bus. the 8051-compatible interface uses the same 8-bit data bus sizing scheme as offered with the m68000 chip selects. as such, there is no restriction on the data operations which can be used?oth byte, word and long transfers can be initiated by the processor to an 8051- compatible device which can have contiguous byte locations. 5.1.3.3 port a, port b general-purpose i/o ports. the mc68307 supports two general purpose i/o ports, port a and port b, whose pins can be configured as general- purpose input/output pins or dedicated peripheral interface pins for the on-chip modules (uart, m-bus, timer, interrupts, peripheral chip selects). port a is an 8-bit i/o port. port b is a 16-bit i/o port. each of the 8 port a and 16 port b pins are independently configured as a general-purpose i/o pin if the corresponding bit in the port a or b control register (pacnt, pbcnt) is cleared. port pins are configured as dedicated on-chip peripheral pins if the corresponding pacnt or pbcnt bit is set. refer to section 5.2.3 external bus interface control registers for details of programming the general-purpose ports. for each port pin, when acting as a general-purpose i/o pin, the signal direction for that pin is determined by the corresponding control bit in the port a or b data direction register (paddr, pbddr). the port i/o pin is configured as an input if the corresponding paddr or pbddr bit is cleared; it is configured as an output if the corresponding paddr or pbddr bit is set. all paddr, pbddr, pacnt, and pbcnt bits are cleared on cold reset,
system integration module motorola mc68307 user? manual 5-11 configuring all port a and b pins as general-purpose inputs. (note that the port pins do not have internal pullup resistors). when a port pin is used as general-purpose i/o, it may be accessed through the port a or b data register (padat, pbdat). data written to the padat or pbdat is stored in an out- put latch. if a port pin is configured as an output, the output latch data is gated onto the port pin. in this case, when the padat or pbdat is read, the contents of the output latch data associated with the output port pin are read. if a port pin is configured as an input, data written to padat or pbdat is still stored in the output latch, but is prevented from reaching the port pin. in this case, when padat or pbdat is read, the current state of the port pin is read. if port pins are selected as dedicated on-chip peripheral pins, the corresponding bit in the paddr or pbddr is ignored, and the actual direction of the pin is determined by the operating mode of the on-chip peripheral. in this case, the padat or pbdat register contains, for those bit positions, the current state of the peripheral's input pin or output driver. the dedicated functions for port a input/output lines are the extra peripheral chip select outputs (cs2b , cs2c , and cs2d ) for simple external peripherals (pa2?a0), the timer output signals tout1 and tout2 (pa4 and pa3), and the bus arbitration signals br , bg, and bgack (pa7?a5). certain port pins may be selected as general-purpose i/o pins, even when other pins related to the same on-chip peripheral are used as dedicated pins. for example, a system which requires a uart interface using txd and rxd signals only, and not requiring rts or cts , is free to program rts /pb4 and cts /pb5 as general-purpose i/o. what the peripheral now receives as input, given that some of its pins have been reassigned, is shown in table 5-2. if an input pin to an i/o peripheral is used as a general-purpose i/o pin, then the actual input to the peripheral is automatically connected internally to v dd or gnd, based on the pin's function. this does not affect the operation of the port i/o pins in their general-purpose i/o function. note also that even if all the pins for a particular peripheral are configured as general-purpose input/output, the peripheral still operates as normal, although this is only useful in the case of the timer module.
system integration module 5-12 mc68307 user? manual motorola the mc68307 port a pins which have alternate functions are shown in table 5-2. the mc68307 port b pins that have alternate functions are shown in table 5-3. the high eight lines of port b (pb15?b8) have as their dedicated function a latched interrupt capability. each of these pins, when configured as a dedicated interrupt input in the port b control register (pbcnt), functions as an active-low input to a latch in the interrupt controller logic (refer to section 5.1.4.1 interrupt controller logic ). as before, even if these pins are configured for their dedicated function, their current state may still be read by software as if they were general-purpose input signals. table 5-2. port a pin functions pacnt bit = 0 pin function pacnt bit = 1 pin function default input to on-chip peripheral pa0 cs2b (output) pa1 cs2c (output) pa2 cs2d (output) pa3 tout1 (output) pa4 tout2 (output) pa5 br 1 pa6 bg (output) pa7 bgack 1 table 5-3. port b pin functions pbcnt bit = 0 pin function pbcnt bit = 1 pin function default input to on-chip peripheral pb0 scl 1 pb1 sda 1 pb2 txd (output) pb3 rxd 1 pb4 rts (output) pb5 cts 1 pb6 tin1 1 pb7 tin2 1 pb8 int1 1 pb9 int2 1 pb10 int3 1 pb11 int4 1 pb12 int5 1 pb13 int6 1 pb14 int7 1 pb15 int8 1
system integration module motorola mc68307 user? manual 5-13 5.1.4 interrupt processing interrupt processing on the mc68307 involves four steps. a typical sequence is as follows: 1. the interrupt controller on the mc68307 collects interrupt events from on and off-chip peripherals, prioritizes them, and presents the highest priority request to the ec000 core processor. 2. the ec000 core processor responds to the interrupt request by executing an interrupt acknowledge bus cycle after the completion of the current instruction. 3. the interrupt controller recognizes the interrupt acknowledge cycle and places the in- terrupt vector for that interrupt request onto the ec000 core processor bus. 4. the ec000 core processor reads the vector, reads the address of the interrupt handler in the exception vector table, and then begins execution at that address. steps 2 and 4 are the responsibility of the ec000 core processor on the mc68307, whereas steps 1 and 3 are the responsibility of the interrupt controller on the mc68307. external devices are forbidden from responding to iack cycles with a vector, this is always done by the interrupt controller. no fc2?c0 signals are available for decode. the ec000 core processor is not modified for use on the mc68307, thus steps 2 and 4 operate exactly as they would on the m68000 devices. in step 2, the ec000 processor status register (sr) is available to mask interrupts globally or to determine which priority levels can currently generate interrupts. also in step 2, the interrupt acknowledge cycle is executed. the interrupt acknowledge cycle carries out a m68000 bus read cycle except that fc2?c0 are encoded as 111, a3?1 are encoded with the interrupt priority level (1?, with 7 (i.e., 111) being the highest), and a19?16 are driven high. this cycle is visible externally, but no chip selects are asserted. in step 4, the ec000 core processor reads the vector number, multiplies it by 4 to get the vector address, fetches a 4-byte program address from that vector address, and then jumps to that 4-byte address. that 4-byte address is the location of the first instruction in the interrupt handler. steps 1 and 3 are the responsibility of the interrupt controller on the mc68307. here a number of configuration options are available. for instance, for step 1 (interrupt generation), all interrupt sources have programmable interrupt priority levels (ipl). in step 3 (vector response), a block of vectors can be allocated to the interrupt sources under program control. these and other interrupt controller options are introduced in the following paragraphs.
system integration module 5-14 mc68307 user? manual motorola 5.1.4.1 interrupt controller logic. this block of logic coordinates all the interrupt sources on the mc68307, gathering interrupt request signals from both the on-chip peripheral modules and external inputs, prioritizing them and performing programmed ipl requests to the ec000 core processor. when the ec000 core processor responds to a request with an interrupt acknowledge cycle, as is standard in m68000 implementations, the interrupt controller logic forwards the correct vector depending on the original source of the interrupt. software can clear pending interrupts from any source via the registers in the interrupt controller logic, and can program the location of the block of vectors used for interrupt sources via the programmable interrupt vector register (pivr). for an external interrupt interface, the interrupt controller logic provides two distinct facilities. first is the nonmaskable interrupt input on the irq7 pin, which always causes an interrupt priority level 7 request to the ec000 core processor. assuming no other source is programmed as a level 7 source, this input always obtains the immediate attention of the core. for an interrupt to be successfully processed, ram must be available for the stack, and often this ram is selected by one of the programmable chip selects. so upon system startup there is a brief period where ram is not available for the stack. to ensure no problems resulting from interrupts (particularly irq7 ) during this period, there is an interlock which prevents any interrupt from reaching the ec000 core processor until the first write cycle to the pivr. the user should ensure that both ram chip selects and the system stack are set up prior to this write operation. the second of the external input methods is an 8-channel latched interrupt port, multiplexed with the port b input/output pins. each of the 8 inputs can be programmed with an ipl, and each can have any pending interrupts cleared independently of the others. the interrupt controller includes daisy-chaining functions in order to avoid contention when the ec000 core processor issues an interrupt acknowledge cycle. so if more than one inter- rupt source has the same ipl, they are daisy-chained in the following priority scheme: irq7 input highest priority int1 ?nt8 inputs timer 1interrupt timer 2 interrupt uart interrupt m-bus interrupt lowest priority the priority within the eight latched interrupt inputs is that int1 is the highest, and int8 is the lowest. the block diagram of the interrupt controller is shown in figure 5-4.
system integration module motorola mc68307 user? manual 5-15 5.1.4.2 interrupt vector generation. pending interrupts are presented to the ec000 core processor in order of priority. the core responds to an interrupt request by initiating an interrupt acknowledge cycle to receive a vector number, which allows the core to locate the interrupt's service routine. the interrupt controller always provides the vector corresponding to the highest priority, unmasked, pending interrupt with the ipl priority equal to that echoed on a3?1 during the iack cycle. the following procedure is used. the four most significant bits of the interrupt vector are programmed by the user in the pivr. these four bits are concatenated with four bits generated by the interrupt controller to provide an 8-bit vector number to the core. the interrupt controller's encoding of the four low-order bits of the interrupt vector is shown in table 5-4. an example vector calculation is shown following table 5-4. when the core initiates an interrupt acknowledge cycle for an interrupt and there is no interrupt pending, the interrupt controller encodes the error code binary 0000 onto the four low-order bits of the interrupt vector to indicate a spurious interrupt. as the interrupt controller responds to all interrupt acknowledge cycles, there will never be a bus error during such cycles, and the ec000 core vector number 24 (spurious interrupt by bus error) will never be used. figure 5-4 shows the interrupt controller logic block diagram. figure 5-4. interrupt controller logic block diagram irq7 input pin int1 ?nt8 input pins on-chip irq's (t1,t2,mb,ua) iack to uart iack daisy-chain iack cycle decode priority control registers d15?0 fc2? a23?0 ctrl/ipl ec000 core programmable vector output latched interrupt input logic irq7 input logic on-chip peripheral input logic ipl priority encode
system integration module 5-16 mc68307 user? manual motorola 1. formulate 8-bit vector (source is timer 2): * 2. multiply by 4 to get address: 1 0 1 0 1 0 1 1 0 0 = $2ac note that $2ac is in the user interrupt vector area of the exception vector table. v7 v4 was purposely chosen to cause this. 3. read 32-bit value at $2ac and jump: * the uart module handles its own interrupt vector separately, it can be programmed to provide any vector by placing a value into the uart interrupt vector register (uivr). for consistency with the other interrupt sources, this value can be programmed as xxxx1100. table 5-4. interrupt vector response vector interrupt source priority if same ipl programmed xxxx0000 spurious interrupt xxxx0001 irq7 input (highest) xxxx0010 int1 input xxxx0011 int2 input xxxx0100 int3 input xxxx0101 int4 input xxxx0110 int5 input xxxx0111 int6 input xxxx1000 int7 input xxxx1001 int8 input xxxx1010 timer 1 xxxx1011 timer 2 xxxx1100 (reserved for uart) * xxxx1101 m-bus module (lowest) v7?4 4-bit vector v7?5 programmed by software in the programmable interrupt vector register 4-bit vector from table 5-4. 1 0 1 0 1 0 1 1 $2ac 0007 interrupt handler begins at $070302 (24-bit addresses are used on the mc68307) $2ae 0302
system integration module motorola mc68307 user? manual 5-17 5.1.4.3 irq7 non-maskable interrupt. the irq7 input functions as a nonmaskable interrupt (nmi) which always generates a level 7 interrupt to the ec000 core processor. priority level 7 cannot be disabled by the interrupt priority mask in the sr of the ec000 core processor. the interrupt controller logic passes an interrupt from the irq7 signal to the processor. when the processor responds with an interrupt acknowledge cycle for level 7, the interrupt controller issues the appropriate vector. the irq7 input is edge sensitive and subject to two clock falling edges of synchronization before being considered valid. if it is still asserted when a level 7 interrupt handler routine exits (thus bringing the processor priority level below 7) then it is ignored until it negates for one clock period before the next valid assertion. if the software needs to read the state of the irq7 signal then the signal can be connected to an unused general-purpose input/ output pin, configured as an input. an interlock is provided which prevents any interrupt including irq7 from reaching the ec000 core processor until the pivr is first written with a vector range. this allows the user to ensure safety upon system startup before essential resources (e.g., chip selects for ram which contain stack) have been set up. 5.1.4.4 general-purpose interrupt inputs. the eight general-purpose latched interrupt lines, int1 ?nt8 share device pins with the high byte of port b i/o. to enable any or all of these lines as dedicated interrupt inputs, the corresponding bit or bits in the pbcnt must be set to one. as discussed already, the current state of the interrupt pin is always available to software by reading the pbdat, so that an interrupt handler can quickly determine the source of the interrupt (it can also determine this by the vector number). before interrupts are enabled in system initialization software, the required ipl should be programmed into the latched interrupt control registers (licr1 and licr2). each of these 16-bit registers contains the priority setting bits (ipl) for four of the general-purpose interrupt lines, along with pending interrupt reset (pir) bits for each of them, allowing the interrupt response software to clear any pending latched interrupt conditions. note that the pir bits do not clear the source of interrupt; this must either happen automatically (by the interrupting device hardware) after the interrupt condition is presented to the mc68307, or software must explicitly address the device in question, and clear the condition manually. note also that when the ipl is changed for these latched interrupts, the pir bit must also be set. this avoids the possibility of any spurious interrupts occurring. refer to section 5.2.4 interrupt control registers for further details and programming information. if the ipl for any one general-purpose interrupt line is programmed as 000, then that line is effectively disabled. another way to mask a particular interrupt line from causing interrupts, without having to reprogram its priority level in the licrx, is to clear the relevant bit in the pbcnt. when the ec000 runs an interrupt acknowledge cycle in response to the external interrupt condition at a certain ipl, the interrupt controller module provides the appropriate vector as discussed in section 5.1.4.2 interrupt vector generation . user software at the address
system integration module 5-18 mc68307 user? manual motorola pointed to by the respective vector location should respond to the interrupt as appropriate, including setting the pir bit for that general-purpose interrupt input in the relevant licrx register, to indicate end-of-service. refer to section 5.1.4 interrupt processing for a short discussion of daisy-chaining with reference to the external interrupt inputs. note the latched interrupts need to be asserted for 2 clock falling edges before they are considered valid, and are latched. 5.1.4.5 peripheral interrupt handling. the mc68307 on-chip i/o peripherals, consisting of the two timer channels, the uart and the m-bus modules, are all capable of being a source of interrupts. the interrupt controller logic coordinates the reception of interrupt request signals from these three peripherals, the return of acknowledge information with associated daisy-chaining (refer to section 5.1.4 interrupt processing ), and the ultimate providing of vector information to the ec000 core processor. the peripheral interrupt control register (picr) allows the user to define which ipl each of these four peripheral sources will use. the pivr and uivr allow the user to define a particular vector number to be presented when the respective module receives an interrupt acknowledge from the processor via the interrupt controller logic. these interrupt vector registers are initialized upon cold reset with the uninitialized interrupt vector (hex $0f), and must be programmed with the required vector number for normal operation. it is important not to use reserved interrupt vector locations for this purpose, especially the ones used by the mbar and scr register group. in the case of the uart, there are multiple sources within the uart module which can cause an interrupt, e.g., transmit ready, received character/buffer, break change of state. in order to determine which of these should be serviced, the software interrupt handler must read the relevant status register within the uart module. note that the uart module has its own vector register, allowing it to issue any programmed vector in response to an interrupt acknowledge cycle. in the case of the m-bus interface, there are multiple sources within the m-bus module which can cause an interrupt, e.g., byte transferred, slave rx address match, arbitration lost. again, the relevant status register within the m-bus interface module must be read to elaborate on the condition being reported. finally, in the case of the timer module, there are multiple sources which can cause an interrupt, e.g., compare or capture for each of the two functional timer channels. the timer event registers can be read to determine the cause of the condition.
system integration module motorola mc68307 user? manual 5-19 5.1.5 low-power sleep logic various options for power-saving are available?urning off unused peripherals, reducing processor clock speed, disabling the processor altogether, or a combination of these. the scr includes a clock divider enable bit (cden) which substitutes a divided-down version of the system clock as the clock input to the ec000 core. the division is by a power-of-2, as programmed in the cd2? bits, allowing a 16mhz system clock to be divided down to approximately 64khz. there is also a low-power sleep mode enable (lpen) bit which stops the clock to the ec000 processor altogether after using bus arbitration to turn off the external bus. prior to this happening, the peripherals which are not required can be disabled or their clocks stopped by programming the appropriate registers, thus further reducing power consumption. the mc68307 crystal oscillator is not stopped by these internal modes. for lowest power operation, the external clock source can be slowed or removed altogether by the user. note because bus arbitration is used, the external address, data bus- es and control signals (as , uds , lds , r/w ) are tristated and so should have weak pullups to minimize system power consump- tion. so, various options for power-saving are available?urning off unused peripherals, reducing processor clock speed, disabling the processor altogether, or a combination of these. a wakeup from low-power sleep mode can be achieved by causing an interrupt at the interrupt controller logic which continues to run throughout the period of processor sleep. any interrupt source causes a wakeup of the ec000 core processor followed by processing of that interrupt when unmasked in the sr. the wakeup operation involves the internal sleep/wake-up logic restarting the clock to the ec000 core processor and releasing the bus. normal processing resumes with all register contents intact, i.e., the processor continues execution from the address following the low- power enable instruction sequence. interrupt exception processing is initiated for the interrupt which caused the wakeup. after a wakeup, the reset source bits in the scr are set to a value which indicates a wakeup has happened. normally, these bits show the source of the most recent reset of the core processor. a sleep/wakeup sequence does not cause any reset of the static core processor or the on-chip peripherals. user software can issue a reset instruction if any external peripherals require reset after a period of being in sleep mode. the on-chip peripherals can initiate a wake-up, for example, the timer can be set to wake- up after a certain elapsed time, or number of external events, or the uart can cause a wake-up on receiving serial data. the clocks provided to the various internal modules can all be gated off, to further reduce power consumption (refer to section 5.2.1.2 system control register (scr) for details).
system integration module 5-20 mc68307 user? manual motorola in the case of the uart, its clock is restarted automatically by a transition on the rxd pin, so that incoming data is clocked in. when the data has been completely received, then an interrupt from the uart can wake-up the core processor as described above. if the other on-chip modules are required to cause a wake-up (the timer and m-bus), then their clocks should not be gated off in this manner. 5.2 programming model the various modules in the mc68307, including the sim, contain registers which are used to control the modules and provide status information from the modules. most of these registers reside in one 4096-byte range of addresses in the memory map of the ec000 core processor. the only exceptions to this rule are the mbar and the scr. these reside in the initial memory map of the mc68307 overlaying motorola-reserved locations of the exception vector table. table 5-5 shows all mc68307 on-chip locations. table 5-5. mc68307 configuration memory map address system configuration registers $0000f0 reserved?o external bus access $0000f2 module base address register (mbar) $0000f4 system control register (scr) $0000f6 system control register (scr), continued $0000f8 reserved?o external bus access $000fa reserved?o external bus access $0000fc reserved?o external bus access $0000fe reserved?o external bus access address sim module?xternal bus interface registers mbase+$011 do not access byte $010 port a control register (pacnt) mbase+$013 do not access byte $012 port a data direction register (paddr) mbase+$015 do not access byte $014 port a data register (padat) mbase+$016 port b control register (pbcnt) mbase+$018 port b data direction register (pbddr) mbase+$01a port b data register (pbdat) address sim module?nterrupt controller registers mbase+$020 latched interrupt control register 1 (licr1) mbase+$022 latched interrupt control register 2 (licr2) mbase+$024 peripheral interrupt control register (picr) mbase+$027 do not access byte $026 programmable interrupt vector reg (pivr) address sim module?hip select registers mbase+$040 base register 0 (br0) mbase+$042 option register 0 (or0) mbase+$044 base register 1 (br1) mbase+$046 option register 1 (or1) mbase+$048 base register 2 (br2)
system integration module motorola mc68307 user? manual 5-21 a software reset instruction resets only the uart, timer, and m-bus registers. none of the system configuration registers are reset except by a cold reset. mbase+$04a option register 2 (or2) mbase+$04c base register 3 (br3) mbase+$04e option register 3 (or3) address sim module?art module registers mbase+$101 do not access byte $100 uart mode register (umr1, umr2) mbase+$103 do not access byte $102 uart status/clock select reg(usr, ucsr) mbase+$105 do not access byte $104 uart command register (ucr) mbase+$107 do not access byte $106 (read) uart receive buffer (utb, urb) mbase+$107 do not access byte $106 (write) uart transmit buffer (utb, urb) mbase+$109 do not access byte $108 (read) uart input port change register (uipcr) mbase+$109 do not access byte $108 (write) uart control reg (uacr) mbase+$10b do not access byte $10a (read) uart interrupt status reg (uisr) mbase+$10b do not access byte $10a (write) uart interrupt mask reg (uimr) mbase+$10d do not access byte $10c baud rate gen prescaler msb (ubg1) mbase+$10f do not access byte $10e baud rate gen prescaler lsb (ubg2) mbase+$119 do not access byte $118 uart interrupt vector register (uivr) mbase+$11b do not access byte $11a uart register input port (uip) mbase+$11d do not access byte $11c uart output port bit set cmd (uop1) mbase+$11f do not access byte $11e uart output port bit reset cmd (uop0) address sim module?imer module registers mbase+$120 timer mode register 1 (tmr1) mbase+$122 timer reference register 1 (trr1) mbase+$124 timer capture register 1 (tcr1) mbase+$126 timer counter 1 (tcn1) mbase+$129 do not access byte $128 timer event register 1 (ter1) mbase+$12a watchdog reference register (wrr) mbase+$12c watchdog counter register (wcr) mbase+$130 timer mode register 2 (tmr2) mbase+$132 timer reference register 2 (trr1) mbase+$134 timer capture register 2 (tcr2) mbase+$136 timer counter 2 (tcn2) mbase+$139 do not access byte $138 timer event register 2 (ter2) address sim module?-bus module registers mbase+$141 do not access byte $140 m-bus address register (madr) mbase+$143 do not access byte $142 m-bus frequency divider register (mfdr) mbase+$145 do not access byte $144 m-bus control register (mbcr) mbase+$147 do not access byte $146 m-bus status register (mbsr) mbase+$149 do not access byte $148 m-bus data i/o register (mbdr) address sim module?hip select registers
system integration module 5-22 mc68307 user? manual motorola 5.2.1 system configuration and protection registers four reserved long-word entries in the m68000 exception vector table (refer to table 4-5) are used as addresses for internal system configuration registers. these entries are at locations $0f0, $0f4, $0f8, and $0fc. the first entry is the on-chip mbar entry; the second is the on-chip scr entry; the third and fourth entries are reserved for future use by motorola. note that some other manufacturers use these reserved locations for other purposes, for example, a dedicated set of autovector locations for on-chip peripherals. in the mc68307, this concept is replaced by programmable interrupt vectors, which can use any spare block of 16 vector locations, except for the reserved ones. 5.2.1.1 module base address register (mbar). the mbar can be read or written at any time. it is a 16-bit read-write location, and resides in the exception vector table, at address hex $0000f2, in supervisor data space. the mbar cannot be accessed in user data space. the register consists of the high address bits, the compare function code bit, and the function code bits, as shown below. the register should only be accessed with word size instructions. upon a total system reset, the mbar value may be read as $bfff, but this value holds no meaning, and therefore the on-chip peripheral locations cannot be accessed at any address, until the mbar is written by the user. fc2?c0?unction codes this field should be initialized to provide the required function code which is used when the on-chip registers are accessed. the primary function of this field is to allow the user to select whether or not the block of registers should be accessible in supervisor data space only (101b) or user data space only (001b). if both are required, then the cfc bit should be cleared to 0. note do not assign this field to the m68000 core interrupt acknowl- edge space (fc2?c0 = 111). cfc?ompare function codes this bit allows the system configuration logic to determine whether or not the user wishes to restrict the on-chip peripheral registers to access by one function code alone, as spec- ified by the fc2?c0 bits. 0 = the fcx bits in the mbar are ignored. accesses to the mc68307 peripheral reg- isters block occur without comparing the fcx bits. 1 = the fcx bits in the mbar are compared. the address space compare logic uses the fcx bits to detect address matches. mbar $0000f2 15 13 12 11 0 fc2?c0 cfc ba23?a12 reset: 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 read/write supervisor only
system integration module motorola mc68307 user? manual 5-23 ba23?a12?ase addresses this field should be initialized to provide the base address for the block of on-chip periph- eral registers. as only address bits from a12 upwards can be specified, the block of on- chip locations thus resides at an address which is a multiple of 4096. this block can be anywhere in the address space, although should not overlap with the other chip selected areas required in the user's application. 5.2.1.2 system control register (scr). the scr can be read or written at any time by 8-bit, 16-bit or 32-bit transfers. it is a 32-bit read/write location, and resides in the exception vector table, at address hex $0000f4?0000f7, in supervisor data space. the scr cannot be accessed in user data space. the register consists of eight status bits (bits 31?4, also called the system status register), and 24 system control bits. the eight system status bits are normally 0 and are set to 1 by some event in the system. writing a 0 to these locations has no effect; writing a 1 clears the status bit. the meanings of the various bits within this register are described in section 5.2.1.3 system status register bits description and section 5.2.1.4 system control register bits description. 5.2.1.3 system status register bits description. the following paragraphs describe the system status register bits. adc?ddress decode conflict this bit is set when a conflict has occurred in the chip select logic because two or more chip select lines attempt assertion in the same bus cycle. this conflict may be caused by a programming error in which the user-allocated memory areas for each chip select over- lap each other. provided the adce bit is set, if adc is set this causes berr to be assert- ed. if this bit is already set when another address decode conflict occurs, berr is still generated. the chip select logic protects the mc68307 from issuing two simultaneous chip selects by employing a priority system. write a one to this location to clear the status bit. writing a zero has no effect. scr $0000f4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 adc wpv hwt rs1? adce wpve epcs e8051 busw0 busw1 busw2 busw3 reset: 0 0 0 x 0 0 x x 0 0 0 0 busw 1 1 1 read/write supervisor only scr continued $0000f6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hwde hw2? uacw uacd tmcd mbcd lpen cden ckd ebusw cd2? reset: 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 read/write supervisor only
system integration module 5-24 mc68307 user? manual motorola note regardless of the state of the chip select programming, this bit is not set and berr is not asserted for an address decode con- flict occurring during access to a scr. this is provided to guar- antee access to the system configuration registers (mbar and scr) during initialization. wpv?rite-protect violation this bit is set when the ec000 core processor attempts to write to a location that has the rw bit set to zero (read only) in its associated chip select base register. provided the wpve bit is set, berr is asserted on the bus cycle that sets this bit. if wpv and wpve are both set when a second write protect violation occurs, berr is still generated. the chip select is not asserted. write a one to this location to clear the status bit. writing a zero has no effect. hwt?ardware watchdog timeout this status bit is set during a bus error (berr asserted) caused by the hardware watch- dog timeout reaching its timeout period without a dtack being received or generated in- ternally. note that the bus error occurs even if this status bit is already set. write a one to this location to clear the status bit. writing a zero has no effect. rs1?s0 ?reset source indication these bits record the source of the most recent reset condition or wakeup from sleep mode (not including a peripheral reset initiated by the processor running a reset instruc- tion). writing to these bits has no effect on their set value. the valid combinations are as follows (rs1 first, then rs0): 00 = cold reset (power-on) 01 = cold reset (reset/halt input signals) 10 = warm reset (software watchdog timeout) 11 = wakeup from low-power sleep mode (no reset involved) bits 28, 25 and 24?eserved by motorola these status bits are as yet undefined, and may be used for motorola internal test or for future options. as such they may at times have a 1 or a 0 value. do not rely on them being always zero when performing comparisons.
system integration module motorola mc68307 user? manual 5-25 5.2.1.4 system control register bits description. the following paragraphs describe the system control register bits. adce?ddress decode conflict enable this bit is used to enable or disable the automatic bus error condition (berr ) which can be raised when the chip select logic reports an address conflict. 0 = berr is not asserted by a conflict in the chip select logic when two or more chip select lines are programmed to overlap the same area. 1 = berr is asserted by a conflict in the chip select logic when two or more chip select lines are programmed to overlap the same area. after cold reset, this bit defaults to zero, so the automatic bus error is disabled. note when the chip select logic reports an address conflict, the adc bit is set, regardless of the value of adce bit. wpve?rite-protect violation enable this bit is used to enable or disable the automatic bus error condition (berr asserted) which can be raised when the chip select logic reports a write-protect violation. 0 = berr is not asserted when a write protect violation occurs. 1 = berr is asserted when a write protect violation occurs. after cold reset, this bit defaults to zero, so the automatic bus error is disabled. note when the chip select logic reports a write-protect violation, the wpv bit is set, regardless of the value of the wpve bit. epcs?nable peripheral chip selects this bit enables or disables the expansion of chip select 2 and its output pin into 4 individ- ual peripheral chip selects. for description of usage, refer to section 5.1.2.2 peripheral chip selects . 0 = the cs2 /cs2a output pin functions as a generic chip select, cs2 . the cs2b /pa0, cs2c /pa1, and cs2d /pa2 pins function as general-purpose input/output pa0, pa1 and pa2, subject to correct programming of the pacnt. 1 = the cs2 /cs2a output pin functions as a the first of four peripheral chip select out- puts, cs2a . the cs2b /pa0, cs2c /pa1, and cs2d /pa2 pins function as the other three peripheral chip select outputs, cs2b , cs2c , cs2d , subject to correct pro- gramming of the pacnt. the block size for this chip select should be 64-kbytes; each output signal selects a 16-kbyte range within the block. if less than four pe- ripheral chip selects are required, they can be individually enabled/disabled in pacnt.
system integration module 5-26 mc68307 user? manual motorola e8051?nable 8051-compatible bus this bit enables or disables the expansion of chip select 3 into an 8051-compatible bus interface, with ale, rd and wr pins indicating the timing of an 8-bit multiplexed lower address/data bus. for description of usage, refer to section 5.1.2.3 8051-compatible bus chip select . 0 = the cs3 output pin functions as a generic m68000-bus chip select. 1 = the cs3 output pin functions as a chip select for the 8051-compatible bus. the ad- dress latch enable output and rd /wr output strobes are active for this bus cycle. each bus cycle has timing which is compatible with 8051 memory and peripherals, rather than m68000 ones. the lower 8 address lines function as a multiplexed ad- dress/data bus. the busw3 bit should be programmed for 8-bit bus width (value zero), as the 8051-compatible bus necessitates an 8-bit data-bus width. busw0?us width for chip-select 0 this bit defines the data bus width (port size) for the memory device selected by cs0 , which is usually the boot rom device. busw0 controls the bus sizing logic whenever cs0 asserts on an address match. 0 = the bus width for cs0-controlled memory accesses is 8-bits. 1 = the bus width for cs0-controlled memory accesses is 16-bits. after cold reset, this bit takes on the logic value which was present on the busw external pin during the reset, thus allowing the boot rom data width to be selected. busw1?us width for chip-select 1 this bit defines the data bus width (port size) for the memory device selected by cs1 . busw1 controls the bus sizing logic whenever cs1 asserts on an address match. 0 = the bus width for cs1-controlled memory accesses is 8-bits. 1 = the bus width for cs1-controlled memory accesses is 16-bits. after cold reset, this bit defaults to one, so the default width for cs1-controlled memory accesses is 16-bits. busw2?us width for chip-select 2 this bit defines the data bus width (port size) for the memory device selected by cs2 and also the four peripheral chip select outputs (cs2a , cs2b , cs2c , cs2d ) if they are en- abled by the epcs bit. busw2 controls the bus sizing logic whenever cs2 asserts on an address match. 0 = the bus width for cs2-controlled memory/peripheral accesses is 8-bits. 1 = the bus width for cs2-controlled memory/peripheral accesses is 16-bits. after cold reset, this bit defaults to one, so the default width for cs2-controlled memory accesses is 16-bits. busw3?us width for chip-select 3 this bit defines the data bus width (port size) for the m68000 memory device selected by cs3 . busw3 controls the bus sizing logic whenever cs3 asserts on an address match.
system integration module motorola mc68307 user? manual 5-27 note that if the 8051-compatible bus is enabled by the e8051 bit, then cs3 accesses are required to be an 8-bit data-bus size, and so this bit should be cleared. 0 = the bus width for cs3-controlled memory accesses is 8-bits. 1 = the bus width for cs3-controlled memory accesses is 16-bits. after cold reset, this bit defaults to one, so the default width for cs3-controlled m68000 memory accesses is 16-bits. hwde?ardware watchdog enable 0 = the hardware watchdog is disabled. 1 = the hardware watchdog is enabled. after cold reset, this bit defaults to one to enable the hardware watchdog. hw2?w0?ardware watchdog count 2? 000 = berr is asserted after 128 clock cycles (8 m s, 16mhz clock) 001 = berr is asserted after 256 clock cycles (16 m s, 16mhz clock) 010 = berr is asserted after 512 clock cycles (32 m s, 16mhz clock) 011 = berr is asserted after 1k clock cycles (64 m s, 16mhz clock) 100 = berr is asserted after 2k clock cycles (128 m s, 16mhz clock) 101 = berr is asserted after 4k clock cycles (256 m s, 16mhz clock) 110 = berr is asserted after 8k clock cycles (512 m s, 16mhz clock) 111 = berr is asserted after 16k clock cycles (1 ms, 16mhz clock) after cold reset, these bits default to all ones; thus, berr is asserted after 1 ms for a 16- mhz system clock. note successive timeouts of the hardware watchdog may vary slightly in length. the counter resolution is 16 clock cycles.
system integration module 5-28 mc68307 user? manual motorola uacw?art clock wakeup setting this bit allows a transition on the rxd pin of the uart to cause an automatic re- start of the uart clock, allowing it to receive a character, even when the uart had its clock stopped by the setting of the uacd bit. if the uart is configured to cause an inter- rupt on rx character or framing error, and the uart interrupt is enabled in the peripheral interrupt control register, then the reception of a character causes an interrupt and a wakeup of the ec000 core processor if it was in low-power mode (as enabled by the lpen bit). 0 = a transition on rxd does not restart the uart clock if disabled by uacd. 1 = a transition on rxd restarts the uart clock if disabled by uacd. after a cold reset, this bit is cleared. note that software should also handle framing errors if this feature is used, in order to avoid spurious transitions on rxd causing unnecessary power consumption. if interrupt on framing error is not enabled in this situation, then the uart module remains active even if the ec000 core is in low-power mode. the interrupt handler would normally set the uart and ec000 core back into low-power mode. uacd?art clock disable setting this bit disables the clock to the uart module immediately. as such it should only be done when no essential data is being transmitted or received by the uart channel. 0 = the clock to the uart module is active. 1 = the clock to the uart module is disabled. after a cold reset, this bit is cleared, and so the uart clock is active. refer also to the description of the uart clock wakeup (uacw bit above). tmcd?imer clock disable setting this bit disables the clock to the timer module immediately. as such it should only be done when no software task depends on a timer channel timeout for completion, de- pending on the user's application. 0 = the clock to the timer module is active. 1 = the clock to the timer module is disabled. after a cold reset, this bit is cleared, and so the timer clock is active. mbcd?-bus clock disable setting this bit disables the clock to the m-bus module immediately. as such it should only be done when no essential data is being transmitted or received by the m-bus channel. 0 = the clock to the m-bus module is active. 1 = the clock to the m-bus module is disabled. after a cold reset, this bit is cleared, and so the m-bus clock is active. lpen?ow-power sleep mode enable setting this bit allows the ec000 core processor to be placed into the low-power sleep mode, stopping its clock input and holding the processor in a known state ready for wake- up as described previously. the sequence for user software to stop the ec000 core clock
system integration module motorola mc68307 user? manual 5-29 is first to set the lpen bit and then to issue a stop instruction immediately to place the processor in a known state. 0 =the cpu clock is to be maintained at the programmed frequency. 1 =the cpu should be shut down as the following stop instruction is executed. the sleep/wake-up logic coordinates the re-awakening operation when it receives an interrupt from any source. the stop instruction should unmask all interrupts so that the processor will exit from the stop on wakeup. after either cold reset or wakeup, this bit is cleared in hardware, and so the processor clock runs. note that for minimum power consumption, any unused peripherals can have their clocks stopped as well, using the uacd, mbcd, ckd and tmcd bits. all these bits should be programmed in one write cycle. refer to section 5.1.5 low-power sleep log- ic for further details. cden?lock divider enable setting this bit allows the internal clock signal for the ec000 core processor to be reduced in frequency as programmed in the cd2?d0 bits. 0 =the cpu clock is to be maintained at the full operating frequency of the system clock input. 1 =the cpu clock should be maintained with a reduced frequency as programmed in the clock divider bits (cd2?d0). after a cold reset, this bit is cleared, so the ec000 core runs at full speed. this bit is un- affected by a wake-up, hence if the ec000 core enters sleep mode with a reduced clock frequency it will wake-up with the same reduced clock frequency. note that the lpen bit always overrides the cden/cd2?d0 setting. ckd?lock-output disable this bit allows the mc68307 clkout pin to be disabled after reset, if it is not required externally. turning this driver off effectively saves power and reduces potential rfi prob- lems. 0 = the clkout pin is enabled. the system clock frequency is available. 1 = the clkout pin is disabled, and is driven permanently high. after cold reset, this bit defaults to zero, thus the clkout pin is active. ebusw?us width for non-chip-select cycles with external dtack this bit defines the data bus width (port size) for bus cycles which do not match any of the programmable chip selects or internal locations, and therefore require an external dtack to terminate the cycle. 0 = the bus width for non-chip-selected memory accesses is 8-bits. 1 = the bus width for non-chip-selected memory accesses is 16-bits. after cold reset, this bit defaults to one, so the default width for non-chip-selected memory accesses is 16-bits. bit 3?eserved by motorola this control bit is as yet undefined, and may be used for motorola internal test or for future derivative products. leave its value as zero always.
system integration module 5-30 mc68307 user? manual motorola cd2?d0?ow-power clock divider ratio program these bits to specify the frequency of clock signal for the ec000 core processor when cpu clock division is enabled by the cden bit. after a cold reset , these bits are cleared, so the ec000 core would run at half the system clock frequency, if the cden bit was set. these bits are unaffected by wake-up. for main low-power sleep (lpen) operation, the cd2?d0 and cden bit values are ignored. note the clock divider ratio should only be changed from one divider value to another when the cden bit is zero, i.e. when the cpu is operating at full speed. changing from one reduced speed to another is not recommended. 5.2.2 chip select registers each of the four chip select units has two registers that define its specific operation. these registers are a 16-bit base register (br) and a 16-bit option register (or) (e.g., br0 and or0). these registers may be modified by the ec000 core. the br should normally be programmed after the or since the br contains the chip select enable bit. programming both registers at once using a long word write is also recommended. 5.2.2.1 base registers (br3?r0). these 16-bit registers consist of a base address field, a read-write bit, a function code field and an enable bit. fc2?c0?unction code field these bits are used to set the address space function code. the address compare logic uses these bits to determine whether an address match exists within its address space and, therefore, whether to assert the chip select line. although the fc2?c0 signals are value division ratio frequency from 16mhz extal 000 2 ~8mhz 001 4 ~4mhz 010 8 ~2mhz 011 16 ~1mhz 100 32 ~512khz 101 64 ~256khz 110 128 ~128khz 111 256 ~64khz br0, br1, br2, br3 mbase+$040, $044, $048, $04c 15 13 12 2 1 0 fc2 fc1 fc0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 rw en reset: 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 read/write supervisor or user
system integration module motorola mc68307 user? manual 5-31 not available externally on the mc68307, they are still available internally for comparison purposes. 111 = not supported; reserved. chip select does not activate if this value is used 110 = value may be used ? 000 = value may be used after system reset, the fcx field in br3?r0 defaults to supervisor program space (fc=110) to select a rom device containing the reset vector. because of the priority mechanism and the enable (en) bit, only the cs0 line is active after a system reset. note the fcx bits can be masked and ignored by the chip select logic using the compare function code bit (cfc) in the option register (orx). ba23?a13?ase address these bits are used to set the starting address of a particular address space. the address compare logic uses only a23?13 to cause an address match within its block size. after system reset, the base address defaults to zero to select a rom device on which the reset vector resides. all base address values default to zero on system reset, but, be- cause of the priority mechanism, only cs0 is active. note all address bits can be masked and ignored by the chip select logic through the base address mask in the option register (orx). rw?ead/write this bit, in conjunction with the mask read/write bit (mrw) in the option register (orx), allows a chip select to assert for only read cycles, only write cycles, or both types of cycle. 0 = the chip select line is asserted for read operations only. 1 = the chip select line is asserted for write operations only. after system reset, this bit defaults to zero (read-only operation). note this bit can be masked and ignored by the read-write compare logic, as determined by the mask read/write bit (mrw) in the op- tion register (orx). the line is then asserted for both read and write cycles. on write protect violation cycles (rw=0 and mrw=1), a bus error exception (berr ) is generated if the write protect violation enable bit (wpve) in the scr is set, and the wpv status bit in the scr is set so that the exception handler can determine the reason for bus error.
system integration module 5-32 mc68307 user? manual motorola en?nable this bit enables or disables one of the chip select outputs and its associated dtack gen- erator. this bit can be set in the same write cycle as the setting of other fields. 0 = the chip select line is disabled. 1 = the chip select line is enabled. after system reset, all chip selects are enabled, however only chip select 0 asserts due to the priority mechanism. the chip select does not require disabling before changing its pa- rameters, although care should be taken if altering the configuration of the chip select that is currently asserting on the instruction stream, e.g., to relocate rom to a higher address. it is best to ensure that both base register and option register are written in one long word cycle. 5.2.2.2 option registers (or3?r0). these four 16-bit registers consist of a base address mask field, a read/write mask bit, a compare function code bit, and a dtack generation field. dtack field these bits are used to determine whether dtack is generated internally with a program- mable number of wait states or externally by the peripheral. with internal dtack gener- ation, zero to six wait states can be automatically inserted before the dtack pin is asserted as an output (refer to table 5-6). chip select 3 when used in the 8051-compatible bus mode, has a minimum of 6 and a maximum of 12 wait-states. the meaning of the dtack bits changes accordingly as shown in the table. or0, or1, or2, or3 mbase+$042, $046, $04a, $04e 15 13 12 2 1 0 dtack base address mask (m23?13) mrw cfc reset: 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 read/write supervisor or user table 5-6. dtack field encoding bits m68000-bus cycles description 8051-compatible bus cycles description 15 14 13 0 0 0 no wait state 6 wait states 0 0 1 1 wait state 7 wait states 0 1 0 2 wait states 8 wait states 0 1 1 3 wait states 9 wait states 1 0 0 4 wait states 10 wait states 1 0 1 5 wait states 11 wait states 1 1 0 6 wait states 12 wait states 1 1 1 external dtack external dtack
system integration module motorola mc68307 user? manual 5-33 when all the bits in this field are set to one, dtack must be generated externally, and the mc68307 waits for dtack (input) to terminate its bus cycle. after system reset, the bits of the dtack field default to six wait states (m68000 cycles) or 12 wait states (8051-cycles). the dtack generator uses the mc68307 internal processor clock to generate the pro- grammable number of wait states. the number of wait states remains constant as pro- grammed even if the processor clock speed is reduced using sleep modes. note do not assert dtack externally when it is programmed to be generated internally. the signal is bidirectional, and outputs as an indication of the internally generated signal. m23?13?ase address mask these bits are used to set the block size of a particular chip select line. the address com- pare logic uses only the address bits that are not masked (i.e., mask bit set to one) to de- tect an address match within its block size. 0 = the address bit in the corresponding base register (br) is masked; the address compare logic does not use this address bit. the corresponding external address line value is a don't care in the comparison. 1 = the address bit in the corresponding br is not masked; the address compare logic uses this address bit. for example, for a 64-kbyte block, this field should be m13?15 = 0 with the rest of the base address mask bits (m23?16) equal to one. after system reset, the bits of the base address mask field default to ones, (selecting the smallest block size of 8 kbytes) to allow cs0 to select the rom device containing the re- set vector. mrw?ask read/write this bit is used to disable or enable the comparison of read or write cycle during the chip select matching process. 0 = the read/write bit (rw) in the base register (br) is masked. the chip select is as- serted for both read and write operations. 1 = the rw bit in the br is not masked. the chip select is asserted for read-only or write-only operations as programmed by the corresponding rw bit in br3?r0. after system reset, this bit defaults to zero.
system integration module 5-34 mc68307 user? manual motorola cfc?ompare function code 0 = the function code 2-0 bits (fc2?c0) in the base register (br) are ignored. the chip select is asserted without comparing the fcx bits. 1 = the fcx bits on the br are compared. the address space compare logic uses the fcx bits to assert the csx line. after system reset, this bit defaults to one. note even when cfc=0, if the function code lines are internally gen- erated as ?11?(cpu space cycle), the chip select is not assert- ed. 5.2.3 external bus interface control registers these consist only of the control and data registers associated with the external general- purpose/dedicated i/o signals. all other configuration of the external bus interface is contained within either the system configuration or the chip select logic blocks. 5.2.3.1 port a control register (pacnt). this 8-bit read/write register is used by the user to specify the function of the i/o lines in port a, the 8-bit i/o port, as general-purpose i/o, or dedicated i/o for the on-chip peripherals. from a cold reset, these register bits are all cleared, thus configuring all port a i/o lines as general-purpose inputs. bootstrap software must write an appropriate value into pacnt to reflect the system hardware setup, before any of the peripherals which need port a pins can be used properly. pullup resistors may be required if the dedicated peripheral outputs (which share port a pins) are used, as these signals would otherwise momentarily float at cold reset until configured in the pacnt register. ca7?a0?ort a pin assignment control these bits are used to determine whether the corresponding port a input/output line are configured as general-purpose functions or dedicated functions. 0 = the corresponding port a i/o bit is to be a general-purpose i/o bit. 1 = the corresponding port a i/o bit is to be a dedicated i/o bit. pacnt mbase+$011 7 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user
system integration module motorola mc68307 user? manual 5-35 5.2.3.2 port a data direction register (paddr). this 8-bit read/write register is used by the user to program the general-purpose i/o lines in port a, the 8-bit i/o port, as inputs or outputs. from a cold reset, these register bits are all cleared, configuring all port a i/o lines as general-purpose inputs. bootstrap software must write an appropriate value into paddr if any of the port a lines are required as outputs. pullup resistors may be required to solve the problem of port a i/o lines perhaps floating at cold reset, until paddr is written. they may also be required if the peripheral chip select feature (which shares port a pins) is used, as these signals would otherwise momentarily float at cold reset until configured. da7?a0?ata direction field a these bits are used to determine whether the corresponding port a input/output line are inputs or latched outputs. as such, the ddr bit for any one port a line is ignored unless that port a line is configured as general-purpose i/o in the pacnt. if a particular general- purpose i/o line has its direction changed from an input to an output, the initial data which appears on that pin is the last data written to the latch by the padat register. 0 = the corresponding port a i/o bit is to be an input . 1 = the corresponding port a i/o bit is to be an output . 5.2.3.3 port a data register (padat). this 8-bit read/write register is used by the user to read or write the logic states of the general-purpose i/o lines in port a, the 8-bit i/o port. from a cold reset, these register bits are all cleared, so when any port a lines are configured as outputs, a logic zero appears on those pins, unless padat is written with an initial data value to be written. pa7?a0?ort a data field if the corresponding port a bit is configured as a general-purpose output in the paddr and pacnt, then writing a certain logic value to that bit in the padat register enables that logic level to appear on the output pin. data written is latched internally, even for pins paddr mbase+$013 7 0 da7 da6 da5 da4 da3 da2 da1 da0 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user padat mbase+$015 7 0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user
system integration module 5-36 mc68307 user? manual motorola which are not currently configured as outputs. if a port line is reconfigured from being an input to being an output, then the most recently latched value appears on that pin. if the corresponding port a bit is configured as a general-purpose input in the paddr and pacnt, then the current status of that pin can be read by reading padat and examining the value in that bit position. reading padat bits for pins configured as general-purpose outputs simply returns the output value as stored in the latch. reading padat bits for pins configured as dedicated inputs/outputs for on-chip peripherals returns the current state of the pin, whether it is an input or an output. 1 = the corresponding port a bit (input or output) currently holds a logic 1 (high) value (read cycle) or a logic 1 is to be stored to that bit (write cycle). 0 = the corresponding port a bit (input or output) currently holds a logic 0 (low) value (read cycle) or a logic 0 is to be stored to that bit (write cycle). 5.2.3.4 port b control register (pbcnt). this 16-bit read/write register is used by the user to specify the function of the i/o lines in port b, the 16-bit i/o port, as general- purpose i/o, or dedicated i/o for the on-chip peripherals. from a cold reset, these register bits are all cleared, thus configuring all port b i/o lines as general-purpose inputs. bootstrap software must write an appropriate value into pbcnt to reflect the system hardware setup, before any of the peripherals which need port b pins can be used properly. pullup resistors may be required if the dedicated peripheral outputs (which share port b pins) are used, as these signals would otherwise momentarily float at cold reset until configured in the pbcnt register. cb15?b0?ort b pin assignment control these bits are used to determine whether the corresponding port b input/output line are configured as general-purpose functions or dedicated functions. 0 = the corresponding port b i/o bit is to be a general-purpose i/o bit. 1 = the corresponding port b i/o bit is to be a dedicated i/o bit. 5.2.3.5 port b data direction register (pbddr). this 16-bit read/write register is used by the user to program the general-purpose i/o lines in port b, the 16-bit i/o port, as inputs or outputs. from a cold reset, these register bits are all cleared, configuring all port b i/o lines as general-purpose inputs. bootstrap software must write an appropriate value into pbddr if pbcnt mbase+$016 15 0 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write supervisor or user
system integration module motorola mc68307 user? manual 5-37 any of the port b lines are required as outputs. pullup resistors may be required to solve the problem of port b i/o lines perhaps floating at cold reset, until pbddr is written. bits 15??ata direction field b (db15?b0) these bits are used to determine whether the corresponding port b input/output line are inputs or latched outputs. as such, the ddr bit for any one port b line is ignored unless that port b line is configured as a general-purpose output in the pbcnt. if a particular general-purpose i/o line has its direction changed from an input to an output, the initial data which appears on that pin is the last data written to the latch by the pbdat register. 0 = the corresponding port b i/o bit is to be an input . 1 = the corresponding port b i/o bit is to be an ouput . 5.2.3.6 port b data register (pbdat). this 16-bit read/write register is used by the user to read or write the logic states of the general-purpose i/o lines in port b, the 8-bit i/o port. from a cold reset, these register bits are all cleared, so when any port b lines are configured as outputs, a logic zero appears on those pins, unless pbdat is written with an initial data value to be written. pb7?b0?ort b data field if the corresponding port b bit is configured as a general-purpose output in the pbddr, then writing a certain logic value to that bit in the pbdat register enables that logic level to appear on the output pin. data written is latched internally, even for pins which are not currently configured as outputs. as already mentioned, if a port line is reconfigured from being an input to being an output, then the most recently latched value appears on that pin. if the corresponding port b bit is configured as a general-purpose input in the pbddr, then the current status of that pin can be read by reading pbdat and examining the value in that bit position. reading pbdat bits for pins configured as general-purpose outputs simply returns the output value as stored in the latch. reading pbdat bits for pins con- pbddr mbase+$018 15 0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write supervisor or user pbdat mbase+$01a 15 0 pb15 pb14 pb13 pb12 pb11 pb10 pb9 pb8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write supervisor or user
system integration module 5-38 mc68307 user? manual motorola figured as dedicated inputs/outputs for on-chip peripherals returns the current state of the pin, whether it is an input or an output. 1 = the corresponding port b bit (input or output) currently holds a logic 1 (high) value (read cycle) or a logic 1 is to be stored to that bit (write cycle). 0 = the corresponding port b bit (input or output) currently holds a logic 0 (low) value (read cycle) or a logic 0 is to be stored to that bit (write cycle). 5.2.4 interrupt control registers the following paragraphs describe the interrupt control registers. 5.2.4.1 latched interrupt control registers 1,2 (licr1,licr2). these reg- isters control the interrupt priorities for the external general-purpose latched interrupt input signals, and also allow software to reset any pending interrupts from these lines. there are eight general-purpose latched interrupt inputs altogether, each has four bits assigned to it in these registers. the registers can be read or written at any time. when read, the data re- turned is the last value that was written to the register, with the exception of the reset bits, which are transitory functions. the registers can be accessed by either word (16-bit) or byte (8-bit) data transfer instructions. an 8-bit write to one half of a register leaves the other half intact. pir1?ir8?ending interrupt reset 1? these bits allow the user to clear any pending interrupt on the interrupt input latch for the specified input (int1 ?nt8 ). the action of writing a logic 1 to one of these bit positions clears the latch, so that the interrupt input must be toggled before another interrupt is latched. it is not necessary to subsequently write a logic 0 to 'release' the reset condition, this is done internally. when read, these bits indicate the current value of the latched interrupt, a 1 indicating ac- tive, a zero inactive. these bits also enable a new value of the ipl field to be set. each interrupt channel ig- nores the value written to its intxipl(2?) field unless the corresponding pirx bit is licr1 mbase+$020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pir1 int1ipl(2?) pir2 int2ipl(2?) pir3 int3ipl(2?) pir4 int4ipl(2?) reset: 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 read/write supervisor or user licr2 mbase+$022 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pir5 int5ipl(2?) pir6 int6ipl(2?) pir7 int7ipl(2?) pir8 int8ipl(2?) reset: 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 read/write supervisor or user
system integration module motorola mc68307 user? manual 5-39 set. to avoid altering the ipl field values when only a pending interrupt reset is required, use an and.b, and.w or and.l operation with an immediate value containing ones for the pirx bit positions required to be set, with the corresponding ipl fields set to 111. 1 = the corresponding int1 ?nt8 interrupt latch is cleared, so that a pending interrupt on that line is discarded. the new ipl value for that interrupt source is stored (write cycle). 0 = the corresponding int1 ?nt8 interrupt latch is unaffected. any pending interrupt on that line remains pending. the ipl value for that source remains unchanged (write cycle). int1ipl(2?)?nt8ipl(2?)?nterrupt priority level 1? these bits allow the user to specify the ipl for the corresponding general-purpose latched interrupt input line. when an interrupt occurs, the interrupt controller logic asserts the cor- rect priority code on the ec000 interrupt level inputs, and respond to the subsequent ac- knowledge cycle by outputting the correct vector. the ipl for any of the 8 external interrupt sources int1 ?nt8 can only be changed if the corresponding pirx bit is also written as 1. 000 = the corresponding int1 ?nt8 interrupt line is inhibited and cannot generate interrupts. its state can still be read via the port b registers. 001?11= the corresponding int1 ?nt8 interrupt line is enabled, and can generate an interrupt to the ec000 core processor with the indicated priority level. note do not write a 1 to a pir bit without also supplying the correct ipl2?pl0 value for that interrupt channel. the ipl2?pl0 value is written, and if ?00?is supplied, then that channel is effectively disabled. use the and method as described above. 5.2.4.2 peripheral interrupt control register (picr). this register controls the interrupt priorities for the interrupt signals from the mc68307 internal i/o modules, in the same way as the latched interrupt control registers do so for the external latched interrupt input lines the modules which can provide interrupts to the ec000 core processor are: the m-bus interface module, the timer module (both channels), and the uart interface module. each of these sources has four bits assigned to it in the peripheral interrupt control register. the picr can be read or written at any time. when read, the data returned is the last value that was written to the register. this register can be accessed by either word (16-bit) or byte (8-bit) data transfer instructions. an 8-bit write to one half of the register leaves the other half intact. picr mbase+$024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t1ipl(2?) t2ipl(2?) uaipl(2?) mbipl(2?) reset: x 0 0 0 x 0 0 0 x 0 0 0 x 0 0 0 read/write supervisor or user
system integration module 5-40 mc68307 user? manual motorola interrupt priority level timer 1, timer 2, uart, mbus, t1ipl2?, t2ipl2?, mbipl2?, uaipl2? these bits allow the user to specify the ipl for the corresponding on-chip peripheral mod- ule interrupt input line (timer 1, timer 2, uart and m-bus respectively). when an inter- rupt occurs, the interrupt controller logic asserts the correct priority code on the ec000 interrupt level inputs, and respond to the subsequent acknowledge cycle by coordinating the return of the appropriate vector, as programmed into the programmable interrupt vec- tor register or uart interrupt vector register. 000 = the corresponding interrupt source is inhibited and cannot generate inter- rupts. 001 - 111 =the corresponding interrupt source is enabled, and can generate an inter- rupt to the ec000 core processor with the indicated priority level. the remaining four bits (bits 14, 11, 7, 3) are reserved for future implementation, and should always be written as one. when read, their value should be ignored. 5.2.4.3 programmable interrupt vector register (pivr). this register spec- ifies the vector numbers which is returned by the interrupt controller in response to interrupt acknowledge cycles for the various peripherals and discrete interrupt sources. the high four bits of the vector number are programmed in the pivr, and the low four bits are provided by the interrupt controller depending on the highest priority source which is currently active for the specific ipl being responded to in the current acknowledge cycle. iv7?v4?nterrupt vector numbers 7? these bits provide the high four bits of the interrupt vector for interrupt acknowledge cy- cles from all sources except the uart, which provides its own, unique vector number. the uart has a separate vector register for historical reasons, due to its compatibility with the mc68681 duart. bits 3??nused these bits are ignored on a write cycle, and return 1 on a read cycle. the interrupt con- troller provides the appropriate encoding on these four bits of the vector (refer to section 5.1.4.2 interrupt vector generation ). after cold reset, this register contains the value $0f, although no interrupts are ever propagated to the cpu until the pivr is first programmed (not even level 7 interrupts). only write to the pivr after the cpu stack pointer has been set up to point to valid addressable ram, i.e., after the chip selects for ram have been set up. pivr mbase+$027 7 6 5 4 3 2 1 0 iv7 iv6 iv5 iv4 reset: 0 0 0 0 1 1 1 1 read/write supervisor or user
system integration module motorola mc68307 user? manual 5-41 5.3 mc68307 initialization procedure the following paragraphs describe the initialization procedure. 5.3.1 startup?old reset upon cold reset (power-on reset, rstin asserted, reset and halt pins asserted or software watchdog timeout), all external accesses in the first 8k bytes of the memory address space asserts chip select 0, which should be used to enable a boot rom device. before the chip selects can be set up any other way, the mc68307 on-chip register block must be located in its desired memory map slot by programming the module base address register in supervisor data space at address $0000f2. note that accessing this on-chip register does not in any way access the rom on chip select 0, whose address range includes the mbar address. 5.3.2 sim configuration the cold reset routine should configure all of the following sim functions: chip selects, i/o pin function definition and initial value, interrupt controller ipl levels and vector numbers. these are the ?ystem integration?features which would not normally be changed subsequently, although there is nothing to prevent this if required.
motorola mc68307 user? manual 6-1 section 6 dual timer module 6.1 overview the mc68307 includes three timer units: two identical general-purpose timers and a soft- ware watchdog timer. each general-purpose timer consists of a timer mode register (tmr), a timer capture regis- ter (tcr), a 16-bit timer counter (tcn), a timer reference register (trr), and a timer event register (ter). the tmr contains the prescaler value programmed by the user. the soft- ware watchdog timer, which has a watchdog reference register (wrr) and a watchdog counter (wcn), uses a fixed prescaler value. the timer block diagram is shown in figure 6- 1. the two identical general-purpose 16-bit timer units have the following features: maximum period of 16 seconds (at 16.67 mhz) 60-ns resolution (at 16.67 mhz) programmable sources for the clock input, including external clock input capture capability with programmable trigger edge on input pins output compare with programmable mode for the output pins two timers externally cascadable to form a 32-bit timer free run and restart modes the watchdog timer has the following features: 16-bit counter and reference register maximum period of 16.78 seconds (at 16 mhz) 0.5 ms resolution (at 16 mhz) timeout causes reset of the mc68307 (cpu and peripherals). 6.2 module operation the following paragraphs describe the operation of the dual timer module. 6.2.1 general-purpose timer units the clock input to the prescaler may be selected from the system clock (divided by 1 or by 16) or from the corresponding timer input (tin1 or tin2) pin. tin is internally synchronized to the internal clock. the clock input source is selected by the iclk bits of the corresponding thi d t t d ith f m k 4 0 4
dual timer module 6-2 mc68307 user? manual motorola tmr. the prescaler is programmed to divide the clock input by values from 1 to 256. the output of the prescaler is used as an input to the 16-bit counter. the maximum resolution of the timer is one system clock cycle (60ns at 16.67 mhz). the maximum period (when the reference value is all ones) is 268,435,456 cycles (16.78 sec- onds at 16.00 mhz). each timer may be configured to count until a reference is reached and then either start a new time count immediately or continue to run. the free run/restart (frr) bit of the corre- sponding tmr selects each mode. upon reaching the reference value, the corresponding ter bit is set, and an interrupt is issued if the output reference interrupt enable (ori) bit in tmr is set. figure 6-1. timer block diagram timer clock generator divider mode register prescaler mode bits timer counter 15 0 reference register 15 0 capture register 15 0 15 0 70 event reg capture detection system clock or system clock/16 tin1 tout1 tin2 tout2 timer counter 15 0 reference register 15 0 by 256 internal reset system clock/16 timer 1 timer 2 general-purpose timers watchdog timer clock data bus (16) divide interrupt controller
dual timer module motorola mc68307 user? manual 6-3 each timer may output a signal on the timer output (tout1 or tout2) pin when the refer- ence value is reached, as selected by the output mode (om) bit of the corresponding tmr. this signal can be an active-low pulse or a toggle of the current output, under program con- trol. the output can also be used as an input to the other timer, resulting in a 32-bit timer. each timer has a 16-bit tcr, which is used to latch the value of the counter when a defined transition (of tin1 or tin2) is sensed by the corresponding input capture edge detector. the type of transition triggering the capture is selected by the capture edge (ce) bits in the cor- responding tmr. upon a capture or reference event, the corresponding ter bit is set, and a maskable interrupt is issued. 6.2.2 software watchdog timer a software watchdog timer is used to protect against system failures by providing a means to escape from unexpected input conditions, external events, or programming errors. the third 16-bit timer block is used for this purpose. once started, the software watchdog timer must be cleared by software on a regular basis so that it never reaches its timeout value. upon reaching the timeout value, the assumption is made that a system failure has occurred, and the software watchdog logic initiates a reset of the mc68307. the software watchdog timer counts from zero to a maximum of 32768 (16.67 seconds at 16.00 mhz) with a resolution or step size of 8192 clock periods (0.5 ms at 16.00 mhz). this timer uses a 16-bit counter with an 8-bit prescaler value. the software watchdog timer uses the system clock divided by 16 as the input to the pres- caler. the prescaler circuitry divides the clock input by a fixed value of 256. the output of this prescaler circuitry is connected to the input of the 16-bit counter. since the least signif- icant bit of the wcn is not used in the comparison with the wrr reference value, the effec- tive value of the prescaler is 512. the timer counts until the reference value is reached and then starts a new time count imme- diately. upon reaching the reference value, the counter asserts an internal output to the mc68307 reset logic. the reset source bits (rs1-rs0) in the system control register (scr) are updated with the cause of reset being indicated as software watchdog. refer to section 5.2.1.2 system control register (scr) for further details of the rsx bits. the value of the timer can be read any time.
dual timer module 6-4 mc68307 user? manual motorola 6.3 programming model the following paragraphs describe the programming model of the dual timer module. 6.3.1 general purpose timer units the timer registers may be modified at any time by the user. 6.3.1.1 timer mode register (tmr1, tmr2). tmr1 and tmr2 are identical 16-bit memory-mapped registers. they are cleared by reset. ps?rescaler value the prescaler is programmed to divide the clock input by values from 1 to 256. the value 00000000 divides the clock by 1; the value 11111111 divides the clock by 256. ce1?e0?apture edge and enable interrupt 00 = disable interrupt on capture event 01 = capture on rising edge only and enable interrupt on capture event 10 = capture on falling edge only and enable interrupt on capture event 11 = capture on any edge and enable interrupt on capture event om?utput mode 0 = active-low pulse for one clko clock cycle (60ns at 16.67 mhz) 1 = toggle output ori?utput reference interrupt enable 0 = disable interrupt for reference reached (does not affect interrupt on capture func- tion) 1 = enable interrupt upon reaching the reference value frr?ree run/restart 0 = free run: timer count continues to increment after the reference value is reached. 1 = restart: timer count is reset immediately after the reference value is reached. iclk1?clk0?nput clock source for the timer 00 = stop count 01 = master system clock 10 = master system clock divided by 16. note that this clock source is not synchronized to the timer; thus, successive timeouts may vary slightly in length. 11 = corresponding tin pin, tin1 or tin2 (falling edge) tmr1 tmr2 mbase+$120 mbase+$130 15 8 7 6 5 4 3 2 1 0 prescaler value (ps7?) ce1?e0 om ori frr iclk1?clk0 rst reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write supervisor or user
dual timer module motorola mc68307 user? manual 6-5 rst?eset timer this bit performs a software reset of the timer similar to that of an external reset, although while this bit is zero, the other register values can still be written. effectively, a transition of this bit from one to zero is what resets the register values. the counter/timer/prescaler is not clocked unless the timer is enabled. 0 = reset timer (software reset) 1 = enable timer note after reset, the tout signal begins in a high state, but is not available externally until the port a control register (pacnt) is configured for this function. 6.3.1.2 timer reference registers (trr1, trr2). each trrx is a 16-bit register containing the reference value that is compared with the free-running tcn as part of the out- put compare function. trr1 and trr2 are memory-mapped read-write registers. trr1 and trr2 are set to all ones by reset. the reference value is not matched until tcn increments to equal trr. 6.3.1.3 timer capture registers (tcr1, tcr2). each tcrx is a 16-bit register used to latch the value of the tcn during a capture operation when an edge occurs on the respective tin1 or tin2 pin, as programmed in the tmr. tcr1 and tcr2 appear as mem- ory-mapped read-only registers to the user and are cleared at reset. 6.3.1.4 timer counter (tcn1, tcn2). tcn1 and tcn2 are 16-bit up-counters. each is memory-mapped and can be read by the user at any time. a read cycle to tcn1 and tcn2 yields the current value of the timer and does not affect the counting operation. trr1 trr2 mbase+$122 mbase+$132 15 0 16-bit reference compare value ref(15?) reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 read/write supervisor or user tcr1 tcr2 mbase+$124 mbase+$134 15 0 16-bit captured counter value cap(15?) reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read-only supervisor or user
dual timer module 6-6 mc68307 user? manual motorola a write cycle to tcn1 and tcn2 causes it and the corresponding prescaler to be reset. 6.3.1.5 timer event registers (ter1, ter2). each terx is an 8-bit register used to report events recognized by any of the timers. on recognition of an event, the timer sets the appropriate bit in the ter, regardless of the corresponding interrupt enable bits (ori and ce) in the tmr. ter1 and ter2, which appear to the user as memory-mapped registers, may be read at any time. a bit is cleared by writing a one to that bit (writing a zero does not affect a bit? value). more than one bit may be cleared at a time. both bits must be cleared before the timer negates the irq to the interrupt controller. this register is cleared at reset. bits 7??eserved by motorola. these bits are currently zero when read. ref?utput reference event the counter has reached the trr value. the ori bit in the tmr is used to enable the interrupt request caused by this event. write a one to this bit to clear the event condition. cap?apture event the counter value has been latched into the tcr. the ce bits in the tmr are used to enable the interrupt request caused by this event. write a one to this bit to clear the event condition. tcn1 tcn2 mbase+$126 mbase+$136 15 0 16-bit timer counter value count(15?) reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write supervisor or user ter1 ter2 mbase+$129 mbase+$139 7 2 1 0 reserved, read as 0 ref cap reset: 0 0 0 0 0 0 0 0 read/write supervisor or user
dual timer module motorola mc68307 user? manual 6-7 6.3.2 software watchdog timer the software watchdog timer module has an 8-bit prescaler that is not accessible to the user, a read-only 16-bit watchdog counter register wcr, and a wrr. 6.3.2.1 watchdog reference register (wrr). the wrr is a 16-bit register con- taining the reference value for the watchdog timeout. the wrr appears as a memory- mapped read-write register to the user. reset initializes the register to $ffff, enabling the watchdog timer and setting it to the max- imum timeout period. this causes a timeout to occur if there is an error in the boot program. reference value this 15-bit field should be written with the limit value for the corresponding wcr count bits. it is 15-bits wide because the least-significant bit of the wcr is not compared. en ?enable watchdog 1 = the watchdog timer is enabled, software should periodically write to the wcr lo- cation, so that the counter never reaches the above reference value. 0 = the watchdog timer is disabled, and does not count. 6.3.2.2 watchdog counter register (wcr). the wcr is a 16-bit up-counter, appears as a memory-mapped register and may be read at any time. clearing en in the wrr causes the counter to be reset and disables the count operation. a read cycle to wcr causes the current value of the watchdog timer to be read. reading the watchdog timer does not affect the counting operation. a write cycle to wcr causes the counter and prescaler to be reset. a write cycle should be executed on a regular basis so that the watchdog timer is never allowed to reach the refer- ence value during normal program operation. wrr mbase+$12a 15 0 15-bit reference value ref(15?) en reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 read/write supervisor or user wcr mbase+$12c 15 0 16-bit counter value count(15?) reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 read/write supervisor or user
dual timer module 6-8 mc68307 user? manual motorola 6.4 timer programming examples the programming examples below are written in m68000 assembly language. they refer to symbolic names of mc68307 registers and bit fields within those registers. for access to on- chip locations, the addressing mode offset_from(a5) is used. below is a list of the bit defi- nitions used in the examples. * tmrx bit definitions (non-zero cases only) rst equ $0001 tmrx rst ; enable timer iclk01 equ $0002 tmrx iclk ; use system clock iclk10 equ $0004 tmrx iclk ; use system clock divide by 16 iclk11 equ $0006 tmrx iclk ; use tinx as clock frr equ $0008 tmrx frr ; restart timer on ref. compare ori equ $0010 tmrx ori ; enable interrupt on ref. compare om equ $0020 tmrx om ; toggle toutx ce01 equ $0040 tmrx ce ; capture on +ve edge clk + interrupt ce10 equ $0080 tmrx ce ; capture on -ve edge clk + interrupt ce11 equ $00c0 tmrx ce ; capture on both clk edges + interrupt * terx bit masks ref equ $02 ; isolate terx ref bit cap equ $01 ; isolate terx cap bit the examples assume that the timer is in a reset state prior to execution of the code sequence, that is, either this is the first timer access after a system reset or the timer mode register rst bit has had a programmed transition from 1 to 0. 6.4.1 initialization and reference compare function this code sequence starts both timers in an output reference compare mode, outputting a repeating pulse on each channel? tout pin after a preset period. the reference value and prescale value have been made different in each case to demonstrate programming of dif- ferent periods. interrupts are disabled in this example. if the ori bit were also set, interrupts would be enabled, one for each corresponding toutx pulse. toutx is also set to output to a single clock pulse on each match. the alternate mode is toggle mode, accomplished by also setting the om bit of tmrx. note that the timer mode registers can be programmed in one operation. there is no need to have separate writes to take the timer out of reset, to program the various modes and then to finally start the clock. * enable timer output pins in port a control register or.b #$18,pacnt(a5) ; tout1, 2 pins67 dedicated * setup timer 1 and timer 2 to run independently of each other * both counters reset (and repeat forever) after reference reached * both disabled interrupts for reference
dual timer module motorola mc68307 user? manual 6-9 * active-low pulses on tout1 and tout2 * both disabled interrupts on capture * tout1 pulse generated every (2 x 9) cpu clocks with no interrupts * timer 1 prescaler: divide by 2, reference: divide by 9 move.w #8,trr1(a5) ; reference value 8 move.w #rst+iclk01+frr+$0100,tmr1(a5); value=$010b * tout2 pulse generated every (3 x 7) cpu clocks with no interrupts * timer 2 prescalar: divide by 3, reference: divide by 7 move.w #6,trr2(a5) ; reference value 6 move.w #rst+iclk01+frr+$0200,tmr2(a5); value=$020b 6.4.2 event counting function and interrupts a variation on the reference compare function demonstrated above is the following example of event counting with an interrupt to the cpu after n events have been counted. note that the reference register is programmed with the compare value before the timer is started, otherwise a spurious compare may occur. although the timer channel is in reset (rst bit = 0), other registers can be accessed. * enable timer 1 input pin in port b control register or.w #$0040,pbcnt(a5) ; tin1 pin dedicated * set up tin1 as clock source; * interrupt generated every 4 tin1 clocks, so reference value = 3 * counter reset after reference reached * enable interrupt for reference * active-low pulse on tout1 * disable interrupt on capture * prescaler: divide by 1 move.w #3,trr1(a5) ; reference value 3 move.w #rst+iclk11+frr+ori,tmr1(a5) ; value=$001f stop $2000 ; wait for irq .... .... .... int_t1;andi.b #ref,ter1(a5) ; clear ref event bit .... .... ; process the interrupt rte 6.4.3 input capture function this example provides an interrupt routine that reads the captured timer value each time the tin2 pin has a transition from 0 to 1. the timer is programmed to be free-running (frr bit not set) and so the reference value is ignored.
dual timer module 6-10 mc68307 user? manual motorola note that the interrupt service routine does not check which event bit is set as the cause of the interrupt. a more robust system would do this, and indeed a timer channel could have both interrupt sources enabled. * enable timer 2 input pin in port b control register or.w #$0080,pbcnt(a5) ; tin2 pin dedicated * capture on tin2 +ve edge using system clock as clock source * get captured timer word in register d5 * counter free-running * disable interrupt for reference * enable interrupt on capture on +ve tin2 edge * prescaler: divide by 1 move.w #rst+iclk01+ce01,tmr2(a5); value=$0043 .... .... .... int_t2:andi.b #cap,ter2(a5) ; clear cap event bit move.w tcr2(a5),d5 ; process the interrupt rte 6.4.4 watchdog usage example the first example shows how to disable the watchdog after system reset if it is not required. note that if a reset instruction is executed, the timer module is reset, and so the watchdog is enabled again. * disable watchdog timer forever move.w #$0000,wrr(a5) ; clear wrr en bit the second example shows setting the watchdog timer to timeout every 10ms unless it is periodically reset by software. the watchdog is clocked by the system clock divided by 16, and there is a fixed 8-bit prescaler, so the resulting clock count value increments every 0.24576ms for a 16.67 mhz system clock. the watchdog reference register is programmed to match on a compare value of 40, to give an approximate 10ms timeout. note that the least significant bit of the counter is not com- pared and the corresponding reference register bit must be 1 to enable the watchdog. * program watchdog for 10ms timeout move.w #$0029,wrr(a5) ; enable = 1, timeout = 40 .... .... .... move.w d0,wcr ; tickle watchdog counter note that it does not matter what data value is written to the wcr to keep it from timing out. the example uses d0 as the source, since it results in the fastest executing instruction. (the clr instruction on a 68000 reads the location before clearing it.)
motorola mc68307 user? manual 7-1 section 7 m-bus interface module motorola bus (in short: m-bus) is a two-wire, bidirectional serial bus which provides a simple, efficient method of data exchange between devices. it is compatible with the widely-used i 2 c bus standard. this two wire bus minimizes the interconnection between devices and eliminates the need for an address decoder. this bus is suitable for applications which need occasional communications in a short dis- tance among a number of devices. it also provides flexibility that allows additional devices to be connected to the bus for further expansion and system developing. the interface is designed to operate up to 100 kb/s with maximum bus loading and timing. the device is capable of operating at higher baud rates, with reduced bus loading. the max- imum communication length and number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. m-bus system is a true multi-master bus including collision detection and arbitration to pre- vent data corruption if two or more masters attempt to control the bus simultaneously. this feature provides the capability for complex applications with multi-processor control. it may also be used for rapid testing and alignment of end products via external connections to an assembly-line computer. the m-bus module has the following key features: compatible with i 2 c bus standard multi-master operation software programmable for one of 32 different serial clock frequencies software selectable acknowledge bit interrupt driven byte by byte data transfer arbitration lost interrupt with automatic mode switching from master to slave calling address identification interrupt start and stop signal generation/detection repeated start signal generation acknowledge bit generation/detection bus busy detection a block diagram of the complete m-bus module is shown in figure 7-1. thi d t t d ith f m k 4 0 4
m-bus interface module 7-2 mc68307 user? manual motorola 7.1 m-bus system configuration the m-bus system uses a serial data line (sda) and a serial clock line (scl) for data trans- fer. all devices connected to it must have open drain or open collector outputs. the logical and function is exercised on both lines with pull-up resistors. 7.2 m-bus protocol normally, a standard communication is composed of four parts: start signal, slave address transmission, data transfer, and stop signal. they are described briefly in the fol- lowing sections and illustrated in figure 7-2. figure 7-1. m-bus interface block diagram registers & m68000 bus interface input sync in/out data shift register address compare scl sda irq addr data clock control start, stop & arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux
m-bus interface module motorola mc68307 user? manual 7-3 7.2.1 start signal when the bus is free, i.e., no master device is engaging the bus (both scl and sda lines are at logical high), a master may initiate communication by sending a start signal. as shown in figure 7-2, a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves. 7.2.2 slave address transmission the first byte of data transfer immediately after the start signal is the slave address transmitted by the master. this is a seven bits long calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. only the slave with a calling address that matches the one transmitted by the master responds by sending back an acknowledge bit. this is done by pulling the sda low at the 9th clock (refer to figure 7-2). 7.2.3 data transfer once successful slave addressing is achieved, the data transfer can proceed byte by byte in a direction specified by the r/w bit previously sent by the calling master. each data byte is 8 bits long. data may be changed only while scl is low and must be held stable while scl is high as shown in figure 7-2. there is one clock pulse on scl for each data bit, the msb being transferred first. each data byte has to be followed by an acknowl- figure 7-2. m-bus transmission signals scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write
m-bus interface module 7-4 mc68307 user? manual motorola edge bit, which is signalled from the receiving device by pulling the sda low at the 9th clock. so one complete data byte transfer needs 9 clock pulses. if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. if the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so that the slave should release the sda line for the mas- ter to generate stop or start signal. 7.2.4 repeated start signal as shown in figure 7-2, a repeated start signal is to generate a start signal without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/ receive mode) without releasing the bus. 7.2.5 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-high transition of sda while scl at logical high. (refer to figure 7-2). 7.2.6 arbitration procedure m-bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock synchronization proce- dure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic ??while another master transmits logic ?? the losing masters immediately switch over to slave receive mode and stop driving sda output. in this case the transition from master to slave mode does not generate a stop condition. meanwhile, a status bit is set by hardware to indicate lost of arbitration. 7.2.7 clock synchronization since wire-and logic is performed on scl line, a high-to-low transition on scl line affects all the devices connected on the bus. the devices start counting their low period and once a device's clock has gone low, it holds the scl line low until the clock high state is reached. however, the change from low to high in this device clock may not change the state of the scl line if another device clock is still within its low period. therefore, synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (refer to figure 7-3). when all devices concerned have counted off their low period, the synchronized clock scl line is released and is pulled high. there is then no difference between the device clocks and the state of the scl line and all the devices start counting their high periods. the first device to complete its high period pulls the scl line low again.
m-bus interface module motorola mc68307 user? manual 7-5 7.2.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byte transfer (9 bits). in such case, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 7.2.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 7.3 programming model there are five registers used in the m-bus interface and the internal configuration of these registers is discussed in the following paragraphs. a block diagram of the m-bus module is shown in figure 7-1. figure 7-3. m-bus clock synchronization scl1 scl2 scl internal counter reset wait start counting high period
m-bus interface module 7-6 mc68307 user? manual motorola 7.3.1 m-bus address register (madr) adr7?dr1?lave address this field contains the specific slave address to be used by the m-bus module. bit 0?eserved by motorola. 7.3.2 m-bus frequency divider register (mfdr) bits 7??eserved by motorola. mbc4?bc0?-bus clock rate 4? this field is used to prescale the clock for bit rate selection. due to the potential slow rise and fall times of the scl and sda signals the bus signals are sampled at the prescaler frequency. this sampling incurs an overhead of 6 clocks per scl pulse. the serial bit clock frequency is equal to the cpu clock divided by the divider shown in table 7-1 plus the sampling overhead of 6 clocks per cycle. for a 16.67 mhz internal operating frequency, the serial bit clock frequency of m-bus ranges from 3825 hz to 595 khz. madr mbase+$141 7 1 0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user mfdr mbase+$143 7 6 5 4 3 2 1 0 mbc4 mbc3 mbc2 mbc1 mbc0 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user
m-bus interface module motorola mc68307 user? manual 7-7 7.3.3 m-bus control register (mbcr) men?-bus enable this bit controls the software reset of the entire m-bus module. 1 = the m-bus module is enabled. this bit must be set before any other mbcr bits have any effect. 0 = the module is reset and disabled. this is the power-on reset situation. when low the interface is held in reset but registers can still be accessed. if the m-bus module is enabled in the middle of a byte transfer the interface behaves as follows. slave mode ignores the current transfer on the bus and start operating whenever a subsequent start condition is detected. master mode is not aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. this would ultimately result in either the current bus master or the m-bus module losing arbi- tration, after which bus operation would return to normal. table 7-1. m-bus prescaler values mbc4?bc0 divider mbc4?bc0 divider 00000 22 10000 352 00001 24 10001 384 00010 28 10010 448 00011 34 10011 544 00100 44 10100 704 00101 48 10101 768 00110 56 10110 896 00111 68 10111 1088 01000 88 11000 1408 01001 96 11001 1536 01010 112 11010 1792 01011 136 11011 2176 01100 176 11100 2816 01101 192 11101 3072 01110 224 11110 3584 01111 272 11111 4352 mbcr mbase+$145 7 6 5 4 3 2 1 0 men mien msta mtx txak rsta reset: 0 0 0 0 0 0 0 0 read/write supervisor or user
m-bus interface module 7-8 mc68307 user? manual motorola mien?-bus interrupt enable 1 = interrupts from the m-bus module are enabled. an m-bus interrupt occurs provided the mif bit in the status register is also set. 0 = interrupts from the m-bus module are disabled. note that this does not clear any currently pending interrupt condition. msta?aster/slave mode select bit upon reset, this bit is cleared. when this bit is changed from 0 to 1, a start signal is generated on the bus, and the master mode is selected. when this bit is cleared, a stop signal is generated and the operation mode changes from master to slave. msta is cleared without generating a stop signal when the master loses arbitration. 1 = master mode 0 = slave mode mtx?ransmit/receive mode select bit this bit selects the direction of master and slave transfers. when addressed as a slave this bit should be set by software according to the srw bit in the status register. in master mode this bit should be set according to the type of transfer required. hence for address cycles this bit is always high. 1 = transmit 0 = receive txak?ransmit acknowledge enable this bit specifies the value driven onto sda during acknowledge cycles for both master and slave receivers. 1 = no acknowledge signal response is sent (i.e., acknowledge bit = 1) 0 = an acknowledge signal is sent out to the bus at the 9th clock bit after receiving one byte data. rsta?epeat start writing a 1 to this bit generates a repeated start condition on the bus, provided we are the current bus master. this bit is always read as a low. attempting a repeated start at the wrong time, if the bus is owned by another master, results in loss of arbitration. 1 = generate repeat start cycle. 0 = do not generate repeat start cycle. bits 1??eserved by motorola.
m-bus interface module motorola mc68307 user? manual 7-9 7.3.4 m-bus status register (mbsr) this status register is read-only with exception of the mif and mal bits, which are software clearable. all bits are cleared upon reset except the mcf and rxak bits. mcf?ata transferring bit while one byte of data is being transferred, this bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. 1 = transfer complete 0 = transfer in progress maas?ddressed as a slave bit when its own specific address (m-bus address register) is matched with the calling ad- dress, this bit is set. the cpu is interrupted provided the mien is set. then the cpu needs to check the srw bit and set its tx/rx mode accordingly. writing to the m-bus control register clears this bit. 1 = addressed as a slave 0 = not addressed as a slave mbb?us busy bit this bit indicates the status of the bus. when a start signal is detected, the mbb is set. if a stop signal is detected, it is cleared. 1 = bus is busy 0 = bus is idle mal?rbitration lost the arbitration lost bit (mal) is set by hardware when the arbitration procedure is lost. ar- bitration is lost in the following circumstances: 1.sda sampled as low when the master drives a high during an address or data trans- mit cycle. 2.sda sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. 3.a start cycle is attempted when the bus is busy. 4.a repeated start cycle is requested in slave mode. 5.a stop condition is detected when the master did not request it. this bit must be cleared by software, writing a low to this bit clears it. bit 3?eserved by motorola. mbsr mbase+$147 7 6 5 4 3 2 1 0 mcf maas mbb mal srw mif rxak reset: 0 0 0 0 0 0 0 0 read/write supervisor or user
m-bus interface module 7-10 mc68307 user? manual motorola srw?lave read/write when maas is set this bit indicates the value of the r/w command bit of the calling ad- dress sent from master. this bit is only valid when a complete transfer has occurred and no other transfers have been initiated. checking this bit, the cpu can select slave trans- mit/receive mode according to the command of master. 1 = slave transmit, master reading from slave. 0 = slave receive, master writing to slave. mif?-bus interrupt the mif bit is set when an interrupt is pending, which causes a processor interrupt re- quest provided mien is set. mif is set when one of the following events occurs: 1.complete one byte transfer (set at the falling edge of the 9th clock). 2.receive a calling address that matches its own specific address in slave receive mode. 3.arbitration lost. this bit must be cleared by software, writing a low to it, in the interrupt routine. rxak?eceived acknowledge the value of sda during the acknowledge bit of a bus cycle. if the rxak is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. if rxak is high, it means no acknowledge signal is detected at the 9th clock. 1 = no acknowledge received 0 = acknowledge received 7.3.5 m-bus data i/o register (mbdr) in master transmit mode, data written into the mbdr is sent to the bus automatically. the most significant bit is sent first. in master receive mode, reading this register initiates next byte data receiving. in slave mode, the same function is available after it is addressed. 7.4 m-bus programming examples the following paragraphs provide programming examples for the m-bus module. 7.4.1 initialization sequence reset puts the m-bus control register to its default status. before the interface can be used to transfer serial data, an initialization procedure must be carried out: 1. update mfdr, select division ratio required to obtain scl frequency from system clock. mbdr mbase+$149 7 0 d7 d6 d5 d4 d3 d2 d1 d0 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user
m-bus interface module motorola mc68307 user? manual 7-11 2. update madr to define its own slave address. 3. set men bit of mbcr to enable the m-bus interface system. 4. modify the bits of mbcr to select master/slave mode, transmit/receive mode, interrupt enable or not. 7.4.2 generation of start after completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. if the device is connected to a multi-master bus system, the state of the m-bus busy bit (mbb) must be tested to check whether the serial bus is free. if the bus is free (mbb=0), the start condition and the first byte (the slave address) can be sent. the data written to the data register comprises the slave calling address and the lsb set to indicate the direction of transfer required from the slave. the bus free time (i.e. the time between a stop condition and the following start condi- tion) is built into the hardware that generates the start cycle. depending on the relative frequencies of the system clock and the scl period it may be necessary to wait until the m- bus is busy after writing the calling address to the mbdr before proceeding with the follow- ing instructions. this is illustrated in the following example. an example of a program which generates the start signal and transmits the first byte of data (slave address) is shown below: chflag btst.b #5,mbsr ; check the mbb bit of the bne.s chflag ; status register. if it is ; set, wait until it is clear txstart bset.b #4,mbcr ; set transmit mode bset.b #5,mbcr ; set master mode ; i.e. generate start condition move.b calling,mbdr ; transmit the calling ; address, d0=r/w mbfree btst.b #5,mbsr ; check the mbb bit of the beq.s mbfree ; status register. if it is ; clear, wait until it is set 7.4.3 post-transfer software response transmission or reception of a byte sets the data transferring bit (mcf) to 1, which indicates one byte communication is finished. also the m-bus interrupt bit (mif) is set, an interrupt is generated if the interrupt function is enable during initialization by setting the mien bit. soft- ware must clear the mif bit in the interrupt routine first. the mcf bit is cleared by reading from the mbdr in receive mode or writing to mbdr in transmit mode. software may service the m-bus i/o in the main program by monitoring the mif bit if the interrupt function is disabled. note that polling should monitor the mif bit rather than the mcf bit since their operation is different when arbitration is lost.
m-bus interface module 7-12 mc68307 user? manual motorola note that when an interrupt occurs at the end of the address cycle the master is always in transmit mode, i.e. the address is transmitted. if master receive mode is required, indicated by r/w bit in mbdr, then the mtx bit should be toggled at this stage. during slave mode address cycles (maas=1) the srw bit in the status register is read to determine the direction of the subsequent transfer and the mtx bit is programmed accord- ingly. for slave mode data cycles (maas=0) the srw bit is not valid, the mtx bit in the con- trol register should be read to determine the direction of the current transfer. the following is an example of a software response by a 'master transmitter' in the interrupt routine (refer to figure 7-4). isr bclr.b #1,mbsr ; clear the mif flag btst.b #5,mbcr ; check the msta flag, beq.s slave ; branch if slave mode btst.b #4,mbcr ; check the mode flag, beq.s receive ; branch if in receive mode btst.b #0,mbsr ; check ack from receiver bne.b end ; if no ack, end of transmission transmit move.b databuf,mbdr ; transmit next byte of data 7.4.4 generation of stop a data transfer ends with a stop signal generated by the master device. a master trans- mitter can simply generate a stop signal after all the data has been transmitted. the fol- lowing is an example showing how a stop condition is generated by a master transmitter. mastx btst.b #0,mbsr ; if no ack, branch to end bne.b end move.b txcnt,d0 ; get value from the ; transmitting counter beq.s end ; if no more data, branch to ; end move.b databuf,mbdr ; transmit next byte of data subi.b #1,txcnt ; decrease the txcnt bra.s emastx ; exit end bclr #5,mbcr ; generate a stop condition emastx rte ; return from interrupt if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (txak) before reading the 2nd last byte of data. before reading the last byte of data, a stop signal must be generated first. the following is an example showing how a stop signal is generated by a master receiver. masr subi.b #1,rxcnt beq.s enmasr ; last byte to be read move.b rxcnt,d1 ; check second last byte subi.b #1,d1 ; to be read bne.s nxmar ; not last one or second last lamar bset.b #3,mbcr ; second last, disable ack ; transmitting bra nxmar
m-bus interface module motorola mc68307 user? manual 7-13 enmasr bclr.b #5,mbcr ; last one, generate 'stop' ; signal nxmar move.b mbdr,rxbuf ; read data and store rte 7.4.5 generation of repeated start at the end of data transfer, if the master still wants to communicate on the bus, it can gen- erate another start signal followed by another slave address without first generate a stop signal. a program example is as shown. restart bset.b #2,mbcr ; another start (restart) move.b calling,mbdr ; transmit the calling ; address, d0=r/w- 7.4.6 slave mode in slave interrupt service routine, the master addressed as slave bit (maas) should be tested to check if a calling of its own address has just been received (refer to figure 7-4). if maas is set, software should set the transmit/receive mode select bit (mtx bit of mbcr) according to the r/w command bit (srw). writing to the mbcr clears the maas automat- ically. note that the only time maas is read as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers clear maas. a data transfer may now be initiated by writing information to mbdr, for slave transmits, or dummy reading from mbdr, in slave receive mode. the slave drives scl low between byte transfers, scl is released when the mbdr is accessed in the required mode. in slave transmitter routine, rxak must be tested before transmitting next byte of data. when rxak is set, this signals 'end of data' from the master receiver, which must then switch from transmitter mode to receiver mode by software. this is followed by a dummy read, which releases the scl line so that the master can generate a stop signal. 7.4.7 arbitration lost only one master can engage the bus at any one time. those devices wishing to engage the bus, but having lost arbitration, switch immediately to slave receive mode by hardware. their data output to the sda line is stopped, but the scl is still generated until the end of the byte during which arbitration was lost. an interrupt occurs at the falling edge of the ninth clock of this transfer with mal=1 and msta=0. if one master attempts to start transmission while the bus is being engaged by another master, the hardware inhibits the transmission; the msta bit is cleared without generating a stop condition; an interrupt to cpu is generated and mal is set to indicate that the attempt to engage the bus failed. in these cases, the slave service routine should test mal first; mal should be cleared by software if it is set.
m-bus interface module 7-14 mc68307 user? manual motorola figure 7-4. flow-chart of typical m-bus interrupt routine read ? read ? clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to mbdr switch to rx mode dummy read from mbdr generate stop signal read data from mbdr and store set txak =1 generate stop signal 2nd last byte to be last byte to be arbitration lost ? clear mal maas=1 ? maas=1 ? srw=1 ? tx/rx ? set tx mode write data to mbdr set rx mode dummy read from mbdr ack from receiver ? tx next byte read data from mbdr and store switch to rx mode dummy read from mbdr rte yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n mif
motorola mc68307 user? manual 8-1 section 8 serial module the mc68307 serial module is a universal asynchronous/synchronous receiver/transmitter that interfaces directly to the cpu. the serial module, shown in figure 8-1, consists of the following major functional areas: serial communication channel sixteen bit timer for baud rate generation internal channel control logic interrupt control logic figure 8-1. simplified block diagram serial communications channel 16-bit timer for baud rate generation internal channel control logic interrupt control logic cts rts rxd txd system clock thi d t t d ith f m k 4 0 4
serial module 8-2 mc68307 user? manual motorola 8.1 module overview features of the serial module are as follows: full-duplex asynchronous/synchronous receiver/transmitter channel quadruple-buffered receiver double-buffered transmitter independently programmable baud rate for receiver and transmitter selectable from: ?timer-generated baud rate up to 260 kbaud programmable data format: ?five to eight data bits plus parity ?odd, even, no parity, or force parity ?nine-sixteenths to two stop bits programmable in one-sixteenth bit increments programmable channel modes: ?normal (full duplex) ?automatic echo ?local loopback ?remote loopback automatic wakeup mode for multidrop applications eight maskable interrupt conditions parity, framing, and overrun error detection false-start bit detection line-break detection and generation detection of breaks originating in the middle of a character start/end break interrupt/status 8.1.1 serial communication channel the communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter using an operating frequency derived from the system clock. the transmitter accepts parallel data from the bus, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits, then outputs a composite serial data stream on the channel transmitter serial data output (txd). refer to section 8.3.2.1 trans- mitter for additional information. the receiver accepts serial data on the channel receiver serial data input (rxd), converts it to parallel format, checks for a start bit, stop bit, parity (if any), or break condition, and trans- fers the assembled character onto the bus during read operations. refer to section 8.3.2.2 receiver for additional information.
serial module motorola mc68307 user? manual 8-3 8.1.2 baud rate generator logic the baud rate generator logic consists of an internal uart clock input which is not avail- able as an external pin, but is a derivative of the imbp system clock, a baud-rate generator (brg) and a programmable 16-bit timer. the clock serves as the basic timing reference for the baud-rate generator and other internal circuits. the 16-bit timer is used to produce a 16x clock for any baud rate by counting down the sys- tem clock, it acts as a programmable divider. this feature is especially useful for non-stan- dard system clock frequencies and baud rates. 8.1.3 baud rate generator/timer the 16-bit timer is used as a baud rate generator, and provides a synchronous clock mode of operation when used as a divide-by-1 clock and an asynchronous clock mode when used as a divide-by-16 clock. this allows flexible baud rates for various system clock rates of the mc68307, the divisor value being directly programmable. 8.1.4 interrupt control logic an internal interrupt request signal (irq ) is provided to notify the mc68307 interrupt control- ler of an interrupt condition. the output is the logical nor of all (up to eight) unmasked inter- rupt status bits in the interrupt status register (uisr). the interrupt level of the serial module is programmed in the mc68307 interrupt controller external to the serial module. when an interrupt at this level is acknowledged, the serial module provides an automatic vector if uart is highest priority at this level. 8.1.5 comparison of serial module to mc68681 the mc68307 is code compatible with the mc68681, except that only channel a is imple- mented, and the timer/counter is used as a baud rate clock, dividing the mc68307 clock fre- quency. the input and output port lines (ipx and opx) are not implemented except for cts and rts functions. 8.2 serial module signal definitions the following paragraphs contain a brief description of the serial module signals. figure 8- 2 shows both the external and internal signal groups. note the terms assertion and negation are used throughout this sec- tion to avoid confusion when dealing with a mixture of active-low and active-high signals. the term assert or assertion indicates that a signal is active or true, independent of the level represent- ed by a high or low voltage. the term negate or negation indi- cates that a signal is inactive or false.
serial module 8-4 mc68307 user? manual motorola 8.2.1 transmitter serial data output (txd) this signal is the transmitter serial data output. the output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. data is shifted out on this signal on the falling edge of the clock source, with the least significant bit transmitted first. note that in order to use the txd signal, the mc68307 port b control register must be set up to enable the corresponding i/o pin for this function. by default this signal functions as port b bit 2. 8.2.2 receiver serial data input (rxd) this signal is the receiver serial data input. data received on this signal is sampled on the rising edge of the clock source, with the least significant bit received first. note that in order to use the rxd, the mc68307 port b control register must be set up to enable the corresponding i/o pin for this function. by default this signal functions as port b bit 3. 8.2.3 request-to-send (rts ) this active-low output signal can be programmed to be automatically negated and asserted by either the receiver or transmitter. when connected to the clear-to-send (cts ) input of a transmitter, this signal can be used to control serial data flow. figure 8-2. external and internal interface signals internal control logic four-character receive buffer two-character transmit buffer input port output port external interface signals interface to cpu serial module internal bus address bus control data 16-bit timer/ baud rate generator sysytem clock irq cts rts rxd txd
serial module motorola mc68307 user? manual 8-5 8.2.4 clear-to-send (cts ) this active-low input is the clear-to-send input. it can generate an interrupt on change-of- state. note that in order to use the rts or cts signals, the mc68307 port b control register must be set up to enable the corresponding i/o pins for these functions. by default these signals function as port b bits 4 and 5 respectively. 8.3 operation the following paragraphs describe the operation of the baud rate generator, transmitter and receiver, and other functional operating modes of the serial module. 8.3.1 baud rate generator/timer the baud rate generator (see figure 8-3) consists of a 16-bit timer clocked by the mc68307 system clock. baud rates are selected by programming a divide value into the 16-bit timer. 8.3.2 transmitter and receiver operating modes the functional block diagram of the transmitter and receiver, including command and oper- ating registers, is shown in figure 8-4. the paragraphs that follow contain descriptions for both these functions in reference to this diagram. for detailed register information, refer to section 8.4 register description and programming figure 8-3. baud rate generator block diagram 16-bit timer baud rate generator clock selectors baud rate generator logic system clock
serial module 8-6 mc68307 user? manual motorola 8.3.2.1 transmitter. the transmitter is enabled through its command register (ucr) located within the serial module. the serial module signals the cpu when it is ready to accept a character by setting the transmitter-ready bit (txrdy) in the uart status register (usr). functional timing information for the transmitter is shown in figure 8-5. the transmitter converts parallel data from the cpu to a serial bit stream on txd. it auto- matically sends a start bit followed by the programmed number of data bits, an optional par- ity bit, and the programmed number of stop bits. the least significant bit is sent first. data is shifted from the transmitter output on the falling edge of the clock source. following transmission of the stop bits, if a new character is not available in the transmitter holding register, the txd output remains high ('mark' condition), and the transmitter empty bit (txemp) in the usr is set. transmission resumes and the txemp bit is cleared when the cpu loads a new character into the transmitter buffer (utb). if a disable command is sent to the transmitter, it continues operating until the character in the transmit shift register, if any, is completely sent out. if the transmitter is reset through a software command, oper- ation ceases immediately (refer to section 8.4.1.5 command register (ucr) ). the trans- mitter is re-enabled through the ucr to resume operation after a disable or software reset. if clear-to-send operation is enabled, cts must be asserted for the character to be trans- mitted. if cts is negated in the middle of a transmission, the character in the shift register figure 8-4. transmitter and receiver functional diagram receiver shift register command register (ucr) w status register (usr) r transmit shift register mode register 1 (umr1) r/w mode register 2 (umr2) r/w transmit holding register w receiver holding register 3 receiver holding register 2 receiver holding register 1 r fifo receive transmit buffer (trb) (2 registers) buffer (urb) (4registers) channel a external interface rxd txd
serial module motorola mc68307 user? manual 8-7 is transmitted, and txd remains in the 'mark' state until cts is asserted again. if the trans- mitter is forced to send a continuous low condition by issuing a send break command, the state of cts is ignored by the transmitter. the transmitter can be programmed to automatically negate the request-to-send (rts ) out- put upon completion of a message transmission. if the transmitter is programmed to operate in this mode, rts must be manually asserted before a message is transmitted. in applica- tions in which the transmitter is disabled after transmission is complete and rts is appro- priately programmed, rts is negated one bit time after the character in the shift register is completely transmitted. the transmitter must be manually re-enabled by reasserting rts before the next message is to be sent. figure 8-5. transmitter timing diagram c1 c2 c3 c4 c6 w ww w ww w w c1 c2 c3 c4 stop break start break c5 not transmitted c6 break c1 in transmission txd transmitter enabled txrdy (sr2) cs cts rts 2 1 notes: 1. timing shown for umr2(4) = 1 2. timing shown for umr2(5) = 1 3. c n = transmit character 4. w = write manually asserted by bit- set command manually asserted
serial module 8-8 mc68307 user? manual motorola 8.3.2.2 receiver. the receiver is enabled through its ucr located within the serial mod- ule. functional timing information for the receiver is shown in figure 8-6. the receiver looks for a high-to-low (mark-to-space) transition of the start bit on rxd. when a transition is detected, the state of rxd is sampled each 16 clock for eight clocks, starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). if rxd is sampled high, the start bit is invalid, and the search for the valid start bit begins again. if rxd is still low, a valid start bit is assumed, and the receiver continues to sample the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. data on the rxd input is sampled on the rising edge of the programmed clock source. the least significant bit is received first. the data is then transferred to a receiver holding register, and the rxrdy bit in the usr is set. if the character length is less than eight bits, the most significant unused bits in the receiver holding register are cleared. after the stop bit is detected, the receiver immediately looks for the next start bit. however, if a non-zero character is received without a stop bit (framing error) and rxd remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit is detected. the parity error (pe), framing error (fe), overrun error (oe), and received break (rb) conditions (if any) set error and break flags in the usr at the received character boundary and are valid only when the rxrdy bit in the usr is set. if a break condition is detected (rxd is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register, and the rb and rxrdy bits in the usr are set. the rxd signal must return to a high condition for at least one-half bit time before a search for the next start bit begins. the receiver detects the beginning of a break in the middle of a character if the break per- sists through the next character time. when the break begins in the middle of a character, the receiver places the damaged character in the receiver first-in-first-out (fifo) stack and sets the corresponding error conditions and rxrdy bit in the usr. then, if the break per- sists until the next character time, the receiver places an all-zero character into the receiver fifo and sets the corresponding rb and rxrdy bits in the usr. 8.3.2.3 fifo stack. the fifo stack is used in the uart's receiver buffer logic. the stack consists of three receiver holding registers. the receive buffer consists of the fifo and a receiver shift register connected to the rxd (refer to figure 8-4). data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the fifo. thus, data flowing from the receiver to the cpu is quadruple buffered. in addition to the data byte, three status bits, pe, fe, and rb, are appended to each data character in the fifo; oe is not appended. by programming the err bit in the channel's mode register (umr1), status is provided in character or block modes. the rxrdy bit in the usr is set whenever one or more characters are available to be read by the cpu. a read of the receiver buffer produces an output of data from the top of the fifo stack. after the read cycle, the data at the top of the fifo stack and its associated status bits are 'popped', and new data can be added at the bottom of the stack by the receiver shift
serial module motorola mc68307 user? manual 8-9 register. the fifo-full status bit (ffull) is set if all three stack positions are filled with data. either the rxrdy or ffull bit can be selected to cause an interrupt. in the character mode, status provided in the usr is given on a character-by-character basis and thus applies only to the character at the top of the fifo. in the block mode, the status provided in the usr is the logical or of all characters coming to the top of the fifo stack since the last reset error command. a continuous logical or function of the corre- sponding status bits is produced in the usr as each character reaches the top of the fifo stack. the block mode is useful in applications where the software overhead of checking each character's error cannot be tolerated. in this mode, entire messages are received, and only one data integrity check is performed at the end of the message. this mode allows a data-reception speed advantage, but does have a disadvantage since each character is not individually checked for error conditions by software. if an error occurs within the message, figure 8-6. receiver timing diagram c6, c7, c8 are lost rxd receiver enabled rxrdy (sr0) ffull (sr1) overrun (sr4) rts (op0) 1 status data status data status data cs reset by command uop(0) = 1 c4 c3 c5 c6 c7 c8 c1 c2 notes: 1. timing shown for mr1(7) = 1 2. timing shown for mr1(6) = 0 3. r = read 4. c = received character n rr rr r rr r c1 c2 c3 c4 c5 lost status data
serial module 8-10 mc68307 user? manual motorola the error is not recognized until the final check is performed, and no indication exists as to which character in the message is at fault. in either mode, reading the usr does not affect the fifo. the fifo is 'popped' only when the receive buffer is read. the usr should be read prior to reading the receive buffer. if all three of the fifo's receiver holding registers are full when a new character is received, the new character is held in the receiver shift register until a fifo position is available. if an addi- tional character is received during this state, the contents of the fifo are not affected. how- ever, the character previously in the receiver shift register is lost, and the oe bit in the usr is set when the receiver detects the start bit of the new overrunning character. to support control flow capability, the receiver can be programmed to automatically negate and assert rts . when in this mode, rts is automatically negated by the receiver when a valid start bit is detected and the fifo stack is full. when a fifo position becomes avail- able, rts is asserted by the receiver. using this mode of operation, overrun errors are pre- vented by connecting the rts to the cts input of the transmitting device. note that in order to use the rts or cts signals, the mc68307 port b control register must be set up to enable the corresponding i/o pins for these functions. by default these signals function as port b bits 4 and 5 respectively. if the fifo stack contains characters and the receiver is disabled, the characters in the fifo can still be read by the cpu. if the receiver is reset, the fifo stack and all receiver status bits, corresponding output ports, and interrupt request are reset. no additional characters are received until the receiver is re-enabled. 8.3.3 looping modes the uart can be configured to operate in various looping modes as shown in figure 8-7. these modes are useful for local and remote system diagnostic functions. the modes are described in the following paragraphs with further information available in section 8.4 reg- ister description and programming . the uart's transmitter and receiver should both be disabled when switching between modes. the selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. 8.3.3.1 automatic echo mode. in this mode, the uart automatically retransmits the received data on a bit-by-bit basis. the local cpu-to-receiver communication continues nor- mally, but the cpu-to-transmitter link is disabled. while in this mode, received data is clocked on the receiver clock and retransmitted on txd. the receiver must be enabled, but the transmitter need not be enabled. since the transmitter is not active, the txemp and txrdy bits in usr are inactive, and data is transmitted as it is received. received parity is checked, but not recalculated for transmis- sion. character framing is also checked, but stop bits are transmitted as received. a received break is echoed as received until the next valid start bit is detected.
serial module motorola mc68307 user? manual 8-11 8.3.3.2 local loopback mode. in this mode, txd is internally connected to rxd. this mode is useful for testing the operation of a local serial module channel by sending data to the transmitter and checking data assembled by the receiver. in this manner, correct chan- nel operations can be assured. also, both transmitter and cpu-to-receiver communications continue normally in this mode. while in this mode, the rxd input data is ignored, the txd is held marking, and the receiver is clocked by the transmitter clock. the transmitter must be enabled, but the receiver need not be enabled. 8.3.3.3 remote loopback mode. in this mode, the channel automatically transmits received data on the txd output on a bit-by-bit basis. the local cpu-to-transmitter link is disabled. this mode is useful in testing receiver and transmitter operation of a remote chan- nel. while in this mode, the receiver clock is used for the transmitter. since the receiver is not active, received data cannot be read by the cpu, and the error sta- tus conditions are inactive. received parity is not checked and is not recalculated for trans- mission. stop bits are transmitted as received. a received break is echoed as received until the next valid start bit is detected. figure 8-7. looping modes functional diagram (a) automatic echo (b) local loopback (c) remote loopback disabled disabled disabled disabled rx tx rx tx rx tx txd output rxd input rxd input rxd input txd output txd output disabled disabled cpu cpu cpu disabled disabled
serial module 8-12 mc68307 user? manual motorola 8.3.4 multidrop mode the uart can be programmed to operate in a wakeup mode for multidrop or multiprocessor applications. functional timing information for the multidrop mode is shown in figure 8-8. the mode is selected by setting bits 3 and 4 in mode register 1 (umr1). this mode of oper- ation allows the master station to be connected to several slave stations (maximum of 256). in this mode, the master transmits an address character followed by a block of data charac- ters targeted for one of the slave stations. the slave stations have their channel receivers disabled. however, they continuously monitor the data stream sent out by the master sta- tion. when an address character is sent by the master, the slave receiver channel notifies its respective cpu by setting the rxrdy bit in the usr and generating an interrupt (if pro- grammed to do so). each slave station cpu then compares the received address to its sta- tion address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. slave stations not addressed continue to monitor the data stream for the next address character. data fields in the data stream are separated by an address character. after a slave receives a block of data, the slave station's cpu dis- ables the receiver and initiates the process again. a transmitted character from the master station consists of a start bit, a programmed number of data bits, an address/data (a/d) bit flag, and a programmed number of stop bits. the a/ d bit identifies the type of character being transmitted to the slave station. the character is interpreted as an address character if the a/d bit is set or as a data character if the a/d bit is cleared. the polarity of the a/d bit is selected by programming bit 2 of umr1. umr1 should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer. in multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. if the receiver is disabled, it sets the rxrdy bit and loads the character into the receiver holding register fifo stack provided the received a/d bit is a one (address tag). the character is discarded if the received a/d bit is a zero (data tag). if the receiver is enabled, all received characters are transferred to the cpu via the receiver holding register stack during read operations. in either case, the data bits are loaded into the data portion of the stack while the a/d bit is loaded into the status portion of the stack normally used for a parity error (usr bit 5). fram- ing error, overrun error, and break detection operate normally. the a/d bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. messages in this mode may still contain error detection and correction information. one way to provide error detec- tion, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character.
serial module motorola mc68307 user? manual 8-13 figure 8-8. multidrop mode timing diagram status data status data 1 0 c0 1 addr 1 addr 2 a/d a/d a/d master station 1 0 c0 1 0 addr 1 addr 2 a/d a/d a/d a/d a/d peripheral station umr1(2) = 1 w w w w ww umr1(2) = 0 addr2 addr1 umr1(4:3) = 11 umr1(2) = 1 0 umr1(4?) = 11 addr w r rr rr c0 addr receiver enabled rxd cs txd transmitter enabled txrdy (usr2) cs w enable
serial module 8-14 mc68307 user? manual motorola 8.3.5 bus operation this section describes the operation of the bus during read, write, and interrupt acknowl- edge cycles to the serial module. all serial module registers must be accessed as bytes. 8.3.5.1 read cycles. the serial module is accessed by the cpu with zero wait states, as the mc68307 system clock is also used for the serial module. the serial module responds to reads with byte data on d7?0. reserved registers return logic zero during reads. 8.3.5.2 write cycles. the serial module is accessed by the cpu with zero wait states. the serial module accepts write data on d7?0. write cycles to read-only registers and reserved registers complete in a normal manner without exception processing; however, the data is ignored. 8.3.5.3 interrupt acknowledge cycles. the serial module is capable of arbitrat- ing for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration. the vector number must be provided if interrupt servicing is necessary; thus, the interrupt vector register (uivr) must be initialized. if the uivr is not initialized, a spurious interrupt exception is taken if interrupts are generated. this works in conjunction with the mc68307 interrupt controller, which allows a programmable ipl for the interrupt. 8.4 register description and programming this section contains a detailed description of each register and its specific function as well as flowcharts of basic serial module programming. 8.4.1 register description the operation of the serial module is controlled by writing control bytes into the appropriate registers. a list of serial module registers and their associated addresses is shown in table 8-1. note all serial module registers are only accessible as bytes. the contents of the mode registers (umr1 and umr2), clock-select register (ucsr), and the auxiliary control register (uacr) bit 7 should only be changed after the receiver/transmitter is issued a software reset command?.e., channel operation must be disabled. care should also be taken if the register contents are changed during receiver/transmitter operations, as undesirable results may be produced. in the registers discussed in the following pages, the numbers above the register description represent the bit position in the register. the register description contains the mnemonic for the bit. the values shown below the register description are the values of those register bits after a hardware reset. a value of u indicates that the bit value is unaffected by reset. the read/write status is shown in the last line.
serial module motorola mc68307 user? manual 8-15 8.4.1.1 mode register 1 (umr1). umr1 controls some of the serial module configura- tion. this register can be read or written at any time. it is accessed when the mode register pointer points to umr1. the pointer is set to umr1 by reset or by a set pointer command, using the control register. after reading or writing umr1, the pointer points to umr2. rxrts?eceiver request-to-send control 1 = upon receipt of a valid start bit, rts is negated if the uart's fifo is full. rts is reasserted when the fifo has an empty position available. 0 = the receiver has no effect on rts . this feature can be used for flow control to prevent overrun in the receiver by using the rt s output to control the cts input of the transmitting device. if both the receiver and transmitter are programmed for rts control, rts control is disabled for both since this configuration is incorrect. see section 8.4.1.2 mode register 2 (umr2) for information on programming the transmitter rts control. table 8-1. serial module programming model address register read (r/w = 1) register write (r/w = 0) mbase+$101 mode register (umr1, umr2) mode register (umr1, umr2) mbase+$103 status register (usr) clock-select register (ucsr) mbase+$105 do not access 1 command register (ucr) mbase+$107 receiver buffer (urb) transmitter buffer (utb) mbase+$109 input port change register (uipcr) auxiliary control register (uacr) mbase+$10b interrupt status register (uisr) interrupt mask register (uimr) mbase+$10d baud rate generator prescale msb (ubg1) mbase+$10f baud rate generator prescale lsb (ubg2) do not access 1 mbase+$119 interrupt vector register (uivr) interrupt vector register (uivr) mbase+$11b input port register (uip) do not access 1 mbase+$11d do not access 1 output port bit set cmd (uop1) 2 mbase+$11f do not access 1 output port bit reset cmd (uop0) 2 notes 1. this address is used for factory testing and should not be read. reading this location results in undesired effects and possible incorrect transmission or reception of characters. register contents may also be changed. 2. address-triggered commands. umr1 mbase + $101 7 6 5 4 3 2 1 0 rxrts rxirq err pm1 pm0 pt b/c1 b/c0 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user
serial module 8-16 mc68307 user? manual motorola rxirq?eceiver interrupt select 1 = ffull is the source that generates irq. 0 = rxrdy is the source that generates irq. err?rror mode this bit controls the meaning of the three fifo status bits (rb, fe, and pe) in the usr. 1 = block mode?he values in the channel usr are the accumulation (i.e., the logical or) of the status for all characters coming to the top of the fifo since the last reset error status command for the channel was issued. refer to section 8.4.1.5 com- mand register (ucr) for more information on serial module commands. 0 = character mode?he values in the channel usr reflect the status of the character at the top of the fifo. note err = 0 must be used to get the correct a/d flag information when in multidrop mode. pm1?m0?arity mode these bits encode the type of parity used for the channel (see table 8-2). the parity bit is added to the transmitted character, and the receiver performs a parity check on incom- ing data. these bits can alternatively select multidrop mode for the channel. pt?arity type this bit selects the parity type if parity is programmed by the parity mode bits, and if mul- tidrop mode is selected, it configures the transmitter for data character transmission or ad- dress character transmission. table 8-2 lists the parity mode and type or the multidrop mode for each combination of the parity mode and the parity type bits. table 8-2. pmx and pt control bits pm1 pm0 parity mode pt parity type 0 0 with parity 0 even parity 0 0 with parity 1 odd parity 0 1 force parity 0 low parity 0 1 force parity 1 high parity 1 0 no parity x no parity 1 1 multidrop mode 0 data character 1 1 multidrop mode 1 address character
serial module motorola mc68307 user? manual 8-17 b/c1?/c0?its per character these bits select the number of data bits per character to be transmitted. the character length listed in table 8-3 does not include start, parity, or stop bits. 8.4.1.2 mode register 2 (umr2). umr2 controls some of the serial module configura- tion. it is accessed when the mode register pointer points to umr2, which occurs after any access to umr1. accesses to umr2 do not change the pointer. cm1?m0?hannel mode these bits select a channel mode as listed in table 8-4. see section 8.3.3 looping modes for more information on the individual modes. txrts?ransmitter ready-to-send this bit controls the negation of the rts signal. 1 = in applications where the transmitter is disabled after transmission is complete, setting this bit causes the particular op bit to be cleared automatically one bit time after the characters, if any, in the channel transmit shift register and the transmitter holding register are completely transmitted, including the programmed number of stop bits. this feature is used to automatically terminate transmission of a mes- sage. if both the receiver and the transmitter in the same channel are programmed for rts control, rts control is disabled for both since this is an incorrect configu- ration. 0 = the transmitter has no effect on rts . table 8-3. b/cx control bits b/c1 b/c0 bits/character 0 0 five bits 0 1 six bits 1 0 seven bits 1 1 eight bits umr2 mbase + $101 7 6 5 4 3 2 1 0 cm1 cm0 txrts txcts sb3 sb2 sb1 sb0 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user table 8-4. cmx control bits cm1 cm0 mode 0 0 normal 0 1 automatic echo 1 0 local loopback 1 1 remote loopback
serial module 8-18 mc68307 user? manual motorola txcts?ransmitter clear-to-send 1 = enables clear-to-send operation. the transmitter checks the state of the cts input each time it is ready to send a character. if cts is asserted, the character is trans- mitted. if cts is negated, the channel txd remains in the high state, and the trans- mission is delayed until cts is asserted. changes in cts while a character is being transmitted do not affect transmission of that character. if both txcts and txrts are enabled, txcts controls the operation of the transmitter. 0 = the cts has no effect on the transmitter. sb3?b0?top-bit length control these bits select the length of the stop bit appended to the transmitted character as listed in table 8-5. stop-bit lengths of nine-sixteenth to two bits, in increments of one-sixteenth bit, are programmable for character lengths of six, seven, and eight bits. for a character length of five bits, one and one-sixteenth to two bits are programmable in increments of one-sixteenth bit. in all cases, the receiver only checks for a high condition at the center of the first stop-bit position?.e., one bit time after the last data bit or after the parity bit, if parity is enabled. if an external 1 clock is used for the transmitter, umr2 bit 3 = 0 selects one stop bit, and umr2 bit 3 = 1 selects two stop bits for transmission. table 8-5. sbx control bits sb3 sb2 sb1 sb0 length 6-8 bits length 5 bits 0 0 0 0 0.563 1.063 0 0 0 1 0.625 1.125 0 0 1 0 0.688 1.188 0 0 1 1 0.750 1.250 0 1 0 0 0.813 1.313 0 1 0 1 0.875 1.375 0 1 1 0 0.938 1.438 0 1 1 1 1.000 1.500 1 0 0 0 1.563 1.563 1 0 0 1 1.625 1.625 1 0 1 0 1.688 1.688 1 0 1 1 1.750 1.750 1 1 0 0 1.813 1.813 1 1 0 1 1.875 1.875 1 1 1 0 1.938 1.938 1 1 1 1 2.000 2.000
serial module motorola mc68307 user? manual 8-19 8.4.1.3 status register (usr). the usr indicates the status of the characters in the fifo and the status of the transmitter and receiver. rb?eceived break 1 = an all-zero character of the programmed length has been received without a stop bit. the rb bit is only valid when the rxrdy bit is set. only a single fifo position is occupied when a break is received. further entries to the fifo are inhibited until rxd returns to the high state for at least one-half bit time, which is equal to two suc- cessive edges of the internal or external 1 clock or 16 successive edges of the external 16 clock. the received break circuit detects breaks that originate in the middle of a received character. however, if a break begins in the middle of a character, it must persist until the end of the next detected character time. 0 = no break has been received. fe?raming error 1 = a stop bit was not detected when the corresponding data character in the fifo was received. the stop-bit check is made in the middle of the first stop-bit position. the bit is valid only when the rxrdy bit is set. 0 = no framing error has occurred. pe?arity error 1 = when the with parity or force parity mode is programmed in the umr1, the corre- sponding character in the fifo was received with incorrect parity. when the mul- tidrop mode is programmed, this bit stores the received a/d bit. this bit is valid only when the rxrdy bit is set. 0 = no parity error has occurred. oe?verrun error 1 = one or more characters in the received data stream have been lost. this bit is set upon receipt of a new character when the fifo is full and a character is already in the shift register waiting for an empty fifo position. when this occurs, the charac- ter in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. this bit is cleared by the reset error status command in the ucr. 0 = no overrun has occurred. usr mbase + $103 7 6 5 4 3 2 1 0 rb fe pe oe txemp txrdy ffull rxrdy reset: 0 0 0 0 0 0 0 0 read only supervisor or user
serial module 8-20 mc68307 user? manual motorola txemp?ransmitter empty 1 = the transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). this bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission. 0 = the transmitter buffer is not empty. either a character is currently being shifted out, or the transmitter is disabled. the transmitter is enabled/disabled by programming the tcx bits in the ucr. txrdy?ransmitter ready 1 = the transmitter holding register is empty and ready to be loaded with a character. this bit is set when the character is transferred to the transmitter shift register. this bit is also set when the transmitter is first enabled. characters loaded into the trans- mitter holding register while the transmitter is disabled are not transmitted. 0 = the transmitter holding register was loaded by the cpu, or the transmitter is dis- abled. ffull?ifo full 1 = a character has been received and is waiting in the receiver buffer fifo. 0 = the fifo is not full, but may contain up to two unread characters. rxrdy?eceiver ready 1 = one or more characters has been received and is waiting in the receiver buffer fifo. 0 = the cpu has read the receiver buffer, and no characters remain in the fifo after this read.
serial module motorola mc68307 user? manual 8-21 8.4.1.4 clock-select register (ucsr). the ucsr selects the baud rate clock for the receiver and transmitter. the baud rates listed in table 8-6 and table 8-7 are only valid if an appropriate frequency is used for the mc68307 system clock, for example, 3.6864 mhz. this is not generally the case, and so a more generic method of baud rate generation is provided by the 16-bit timer. in order to use this mode, program the ucsr to the value $dd. rcs3?cs0?eceiver clock select these bits select the baud rate clock for the receiver from a set of baud rates listed in ta- ble 8-6. the baud rate set selected depends upon the auxiliary control register (uacr) bit 7. set 1 is selected if uacr bit 7 = 0, and set 2 is selected if uacr bit 7 = 1. the re- ceiver clock is always 16 times the baud rate shown in this list. ucsr mbase + $103 7 6 5 4 3 2 1 0 rcs3 rcs2 rcs1 rcs0 tcs3 tcs2 tcs1 tcs0 reset: 0 0 0 0 0 0 0 0 write only supervisor or user table 8-6. rcsx control bits rcs3 rcs2 rcs1 rcs0 set 1 set 2 0 0 0 0 50 75 0 0 0 1 110 110 0 0 1 0 134.5 134.5 0 0 1 1 200 150 0 1 0 0 300 300 0 1 0 1 600 600 0 1 1 0 1200 1200 0 1 1 1 1050 2000 1 0 0 0 2400 2400 1 0 0 1 4800 4800 1 0 1 0 7200 1800 1 0 1 1 9600 9600 1 1 0 0 38.4k 19.2k 1 1 0 1 timer timer 1 110 1 111 note: these values are only valid for a 3.6864 mhz mc68307 clock.
serial module 8-22 mc68307 user? manual motorola tcs3?cs0?ransmitter clock select these bits select the baud rate clock for the transmitter from a set of baud rates listed in table 8-7. the baud rate set selected depends upon uacr bit 7. set 1 is selected if uacr bit 7 = 0, and set 2 is selected if uacr bit 7 = 1. the transmitter clock is always 16 times the baud rate shown in this list. table 8-7. tcsx control bits tcs3 tcs2 tcs1 tcs0 set 1 set 2 0 0 0 0 50 75 0 0 0 1 110 110 0 0 1 0 134.5 134.5 0 0 1 1 200 150 0 1 0 0 300 300 0 1 0 1 600 600 0 1 1 0 1200 1200 0 1 1 1 1050 2000 1 0 0 0 2400 2400 1 0 0 1 4800 4800 1 0 1 0 7200 1800 1 0 1 1 9600 9600 1 1 0 0 38.4k 19.2k 1 1 0 1 timer timer 1 110 1 111 note: these values are only valid for a 3.6864 mhz mc68307 clock.
serial module motorola mc68307 user? manual 8-23 8.4.1.5 command register (ucr). the ucr is used to supply commands to the uart. multiple commands can be specified in a single write to the ucr if the commands are not conflicting?.g., reset transmitter and enable transmitter commands cannot be specified in a single command. misc3?isc0?iscellaneous commands these bits select a single command as listed in table 8-8. reset mode register pointer?he reset mode register pointer command causes the mode register pointer to point to umr1. reset receiver?he reset receiver command resets the receiver. the receiver is imme- diately disabled, the ffull and rxrdy bits in the usr are cleared, and the receiver fifo pointer is reinitialized. all other registers are unaltered. this command should be used in lieu of the receiver disable command whenever the receiver configuration is changed because it places the receiver in a known state. reset transmitter?he reset transmitter command resets the transmitter. the transmit- ter is immediately disabled, and the txemp and txrdy bits in the usr are cleared. all other registers are unaltered. this command should be used in lieu of the transmitter dis- able command whenever the transmitter configuration is changed because it places the transmitter in a known state. reset error status?he reset error status command clears the rb, fe, pe, and oe bits (in the usr). this command is also used in the block mode to clear all error bits after a data block is received. reset break-change interrupt?he reset break-change interrupt command clears the delta break (dbx) bits in the uisr. start break?he start break command forces txd low. if the transmitter is empty, the start of the break conditions can be delayed up to one bit time. if the transmitter is active, ucr mbase + $105 7 6 5 4 3 2 1 0 misc2 misc1 misc0 tc1 tc0 rc1 rc0 reset: 0 0 0 0 0 0 0 0 write only supervisor or user table 8-8. miscx control bits misc2 misc1 misc0 command 0 0 0 no command 0 0 1 reset mode register pointer 0 1 0 reset receiver 0 1 1 reset transmitter 1 0 0 reset error status 1 0 1 reset break-change interrupt 1 1 0 start break 1 1 1 stop break
serial module 8-24 mc68307 user? manual motorola the break begins when transmission of the character is complete. if a character is in the transmitter shift register, the start of the break is delayed until the character is transmitted. if the transmitter holding register has a character, that character is transmitted after the break. the transmitter must be enabled for this command to be accepted. the state of the cts input is ignored for this command. stop break?he stop break command causes txd to go high (mark) within two bit times. characters stored in the transmitter buffer, if any, are transmitted. tc1?c0?ransmitter commands these bits select a single command as listed in table 8-9. no action taken?he no action taken command causes the transmitter to stay in its cur- rent mode. if the transmitter is enabled, it remains enabled; if disabled, it remains dis- abled. transmitter enable?he transmitter enable command enables operation of the channel's transmitter. the txemp and txrdy bits in the usr are also set. if the transmitter is al- ready enabled, this command has no effect. transmitter disable?he transmitter disable command terminates transmitter operation and clears the txemp and txrdy bits in the usr. however, if a character is being trans- mitted when the transmitter is disabled, the transmission of the character is completed be- fore the transmitter becomes inactive. if the transmitter is already disabled, this command has no effect. do not use?o not use this bit combination because the result is indeterminate. rc1?c0?eceiver commands these bits select a single command as listed in table 8-10. no action taken?he no action taken command causes the receiver to stay in its current mode. if the receiver is enabled, it remains enabled; if disabled, it remains disabled. receiver enable?he receiver enable command enables operation of the channel's re- ceiver. if the serial module is not in multidrop mode, this command also forces the receiver table 8-9. tcx control bits tc1 tc0 command 0 0 no action taken 0 1 enable transmitter 1 0 disable transmitter 1 1 do not use table 8-10. rcx control bits rc1 rc0 command 0 0 no action taken 0 1 enable receiver 1 0 disable receiver 1 1 do not use
serial module motorola mc68307 user? manual 8-25 into the search-for-start-bit state. if the receiver is already enabled, this command has no effect. receiver disable?he receiver disable command disables the receiver immediately. any character being received is lost. the command has no effect on the receiver status bits or any other control register. if the serial module is programmed to operate in the local loop- back mode or multidrop mode, the receiver operates even though this command is select- ed. if the receiver is already disabled, this command has no effect. do not use?o not use this bit combination because the result is indeterminate. 8.4.1.6 receiver buffer (urb). the receiver buffer contains three receiver holding registers and a serial shift register. the rxd pin is connected to the serial shift register. the holding registers act as a fifo. the cpu reads from the top of the stack while the receiver shifts and updates from the bottom of the stack when the shift register has been filled (see figure 8-4). rb7?b0?hese bits contain the character in the receiver buffer. 8.4.1.7 transmitter buffer (utb). the transmitter buffer consists of two registers, the transmitter holding register and the transmitter shift register (see figure 8-3). the hold- ing register accepts characters from the bus master if the txrdy bit in the channel's usr is set. a write to the transmitter buffer clears the txrdy bit, inhibiting any more characters until the shift register is ready to accept more data. when the shift register is empty, it checks to see if the holding register has a valid character to be sent (txrdy bit cleared). if there is a valid character, the shift register loads the character and reasserts the txrdy bit in the usr. writes to the transmitter buffer when the channel's usr txrdy bit is clear and when the transmitter is disabled have no effect on the transmitter buffer. tb7?b0?hese bits contain the character in the transmitter buffer. urb mbase + $107 7 6 5 4 3 2 1 0 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 reset: 0 0 0 0 0 0 0 0 read only supervisor or user utb mbase + $107 7 6 5 4 3 2 1 0 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 reset: 0 0 0 0 0 0 0 0 write only supervisor or user
serial module 8-26 mc68307 user? manual motorola 8.4.1.8 input port change register (uipcr). the uipcr shows the current state and the change-of-state for the cts pin. bits 7, 6, 5, 3, 2, 1?eserved by motorola. cos?hange-of-state 1 = a change-of-state (high-to-low or low-to-high transition), lasting longer than 25?0 m s has occurred at the corresponding ipx input. when these bits are set, the uacr can be programmed to generate an interrupt to the cpu. 0 = no change-of-state has occurred since the last time the cpu read the uipcr. a read of the uipcr also clears the uisr cos bit. cts ?urrent state starting two serial clock periods after reset, the cts bit reflects the state of the cts pin. if the cts pin is detected as asserted at that time, the cos bit is set, which initiates an interrupt if the iec bit of the uacr register is enabled. 1 = the current state of the cts input is logic one. 0 = the current state of the cts input is logic zero. 8.4.1.9 auxiliary control register (uacr). the uacr selects which baud rate is used and controls the handshake of the transmitter/receiver. brg?aud rate generator set select 1 = set 2 of the available baud rates is selected. 0 = set 1 of the available baud rates is selected. refer to section 8.4.1.4 clock-select register (ucsr) for more information on the baud rates. uipcr mbase + $109 7 6 5 4 3 2 1 0 0 0 0 cos 1 1 1 cts reset: 0 0 0 0 0 1 1 cts read only supervisor or user uacr mbase + $109 7 6 5 4 3 2 1 0 brg ctms2 ctms1 ctms0 iec reset: 0 0 0 0 0 0 0 0 write only supervisor or user
serial module motorola mc68307 user? manual 8-27 ctms2??imer mode and source select table 8-11 shows the timer mode and source select bit fields. iec?nput enable control 1 = uisr bit 7 is set and an interrupt is generated when the cos bit in the uipcr is set by an external transition on the cts input (if bit 7 of the interrupt mask register (uimr) is set to enable interrupts). 0 = setting the corresponding bit in the uipcr has no effect on uisr bit 7. 8.4.1.10 interrupt status register (uisr). the uisr provides status for all poten- tial interrupt sources. the contents of this register are masked by the uimr. if a flag in the uisr is set and the corresponding bit in uimr is also set, the internal interrupt output is asserted. if the corresponding bit in the uimr is cleared, the state of the bit in the uisr has no effect on the output. note the uimr does not mask reading of the uisr. true status is provided regardless of the contents of uimr. the contents of uisr are cleared when the serial module is reset. cos?hange-of-state 1 = a change-of-state has occurred at the cts input and has been selected to cause an interrupt by programming bit 0 of the uacr. 0 = cos bit in the uipcr is not selected. db?elta break 1 = the receiver has detected the beginning or end of a received break. 0 = no new break-change condition to report. refer to section 8.4.1.5 command register (ucr) for more information on the reset break-change interrupt com- mand. rxrdy?eceiver ready or fifo full the function of this bit is programmed by umr1 bit 6. it is a duplicate of either the ffull or rxrdy bit of usr. table 8-11. timer mode and source select bits ctms2 ctms1 ctms0 mode command clock source select command 0 1 1 counter crystal or external clock note: other values are invalid on the mc68307 and should not be used. uisr mbase + $10b 7 6 5 4 3 2 1 0 cos db rxrdy txrdy reset: 0 0 0 0 0 0 0 0 read only supervisor or user
serial module 8-28 mc68307 user? manual motorola txrdy?ransmitter ready this bit is the duplication of the txrdy bit in usr. 1 = the transmitter holding register is empty and ready to be loaded with a character. 0 = the transmitter holding register was loaded by the cpu, or the transmitter is dis- abled. characters loaded into the transmitter holding register when txrdy=0 are not transmitted. 8.4.1.11 interrupt mask register (uimr). the uimr selects the corresponding bits in the uisr that cause an interrupt. if one of the bits in the uisr is set and the corresponding bit in the uimr is also set, the internal interrupt output is asserted. if the corresponding bit in the uimr is zero, the state of the bit in the uisr has no effect on the interrupt output. the uimr does not mask the reading of the uisr. cos?hange-of-state 1 = enable interrupt 0 = disable interrupt db?elta break 1 = enable interrupt 0 = disable interrupt ffull?ifo full 1 = enable interrupt 0 = disable interrupt txrdy?ransmitter ready 1 = enable interrupt 0 = disable interrupt uimr mbase + $10b 7 6 5 4 3 2 1 0 cos db ffull txrdy reset: 0 0 0 0 0 0 0 0 write only supervisor or user
serial module motorola mc68307 user? manual 8-29 8.4.1.12 timer upper preload register (ubg1). this register holds the eight most significant bits of the preload value to be used by the timer in order to provide a given baud rate. the minimum value that can be loaded on the concatenation of ubg1 with ubg2 is $0002. this register is write only and cannot be read by the cpu. 8.4.1.13 timer upper preload register (ubg2). this register holds the eight least significant bits of the preload value to be used by the timer in order to provide a given baud rate. the minimum value that can be loaded on the concatenation of ubg1 with ubg2 is $0002. this register is write only and cannot be read by the cpu. 8.4.1.14 interrupt vector register (uivr). the uivr contains the 8-bit vector number of the internal interrupt. see section 5.1.4.2 interrupt vector generation , ivr7?vr0?nterrupt vector bits this 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. the uivr is reset to $0f, which indicates an uninitialized interrupt condition. see section 5.1.4.2 interrupt vector generation for more information. 8.4.1.15 input port register (uip). the uip register shows the current state of the cts input. cts ?urrent state 1 = the current state of the cts input is logic one. 0 = the current state of the cts input is logic zero. the information contained in this bit is latched and reflects the state of the input pin at the time that the uip is read. note this bit has the same function and value as the uipcr bit 0. uivr mbase + $119 7 6 5 4 3 2 1 0 ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 reset: 0 0 0 0 0 0 0 0 read/write supervisor or user uip mbase + $11b 7 6 5 4 3 2 1 0 cts reset: 1 1 1 1 1 1 1 1 read only supervisor or user
serial module 8-30 mc68307 user? manual motorola 8.4.1.16 output port data registers (uop1, uop0). the rts output is set by performing a bit set command (writing to uop1) and is cleared by performing a bit reset command (writing to uop0). bit set rts ?utput port parallel output 1 = a write cycle to the op bit set command address sets all op bits corresponding to one bits on the data bus. 0 = these bits are not affected by writing a zero to this address. note the output port bits are inverted at the pins, so the rts set bit provides an asserted rts pin. bit reset rts ?utput port parallel output 1 = a write cycle to the op bit reset command address clears all op bits corresponding to one bits on the data bus. 0 = these bits are not affected by writing a zero to this address. 8.4.2 programming the basic interface software flowchart required for operation of the serial module is shown in figure 8-9. the routines are divided into three categories: serial module initialization i/o driver interrupt handling uop1 mbase + $11d 7 6 5 4 3 2 1 0 rts reset: 0 write only supervisor or user uop0 mbase + $11f 7 6 5 4 3 2 1 0 rts reset: write only supervisor or user
serial module motorola mc68307 user? manual 8-31 8.4.2.1 serial module initialization. the serial module initialization routines con- sist of sinit and chchk. sinit is called at system initialization time to check uart oper- ation. before sinit is called, the calling routine allocates two words on the system stack. upon return to the calling routine, sinit passes information on the system stack to reflect the status of the uart. if sinit finds no errors, the receiver and transmitter are enabled. the chchk routine performs the actual checks as called from the sinit routine. when called, sinit places the uart in the local loopback mode and checks for the following er- rors: transmitter never ready receiver never ready parity error incorrect character received 8.4.2.2 i/o driver example. the i/o driver routines consist of inch and outch. inch is the terminal input character routine and gets a character from the receiver. outch is used to send a character to the transmitter. 8.4.2.3 interrupt handling. the interrupt handling routine consists of sirq, which is executed after the serial module generates an interrupt caused by a change-in-break (beginning of a break). sirq then clears the interrupt source, waits for the next change-in- break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 8.5 serial module initialization sequence if the serial capability of the mc68307 is being used, the following steps are required to prop- erly initialize the serial module. note the serial module registers can be accessed by word or byte op- erations, but only the data byte d7?0 is valid. command register (ucr) reset the receiver and transmitter. interrupt vector register (uivr) program the vector number for a serial module interrupt. interrupt mask register (uimr) enable the desired interrupt sources. auxiliary control register (uacr) select baud rate set (brg bit). initialize the input enable control (iec bit). select timer mode and clock source if necessary.
serial module 8-32 mc68307 user? manual motorola clock select register (ucsr) select the receiver and transmitter clock. use timer as source if required. mode register 1 (umr1) if desired, program operation of receiver ready-to-send (rxrts bit). select receiver-ready or fifo-full notification (r/f bit). select character or block error mode (err bit). select parity mode and type (pm and pt bits). select number of bits per character (b/cx bits). mode register 2 (umr2) select the mode of operation (cmx bits). if desired, program operation of transmitter ready-to-send (txrts bit). if desired, program operation of clear-to-send (txcts bit). select stop-bit length (sbx bits). command register (ucr) enable the receiver and transmitter. figure 8-9. serial mode programming flowchart (1 of 5) serial module initiate: channel interrupts save channel status any errors ? enable receiver assert request to send return sinit chk1 enabla y n sinitr call chchk
serial module motorola mc68307 user? manual 8-33 figure 8-9. serial mode programming flowchart (2 of 5) y n chchk place channel in local loopback mode enable transmitter clear status word is transmitter ready ? waited too long ? waited too long ? n y send character to transmitter has character been received ? chchk txchk sndchr rxchk n y n set transmitter- never-ready flag set receiver- never-ready flag a b y
serial module 8-34 mc68307 user? manual motorola figure 8-9. serial mode programming flowchart (3 of 5) b y n n a y a b y n return have framing error ? set framing error flag have parity error ? set parity error flag get character from receiver same as transmitted character ? set incorrect character flag disable transmitter restore to original mode frchk rstchn prchk chrchk
serial module motorola mc68307 user? manual 8-35 figure 8-9. serial mode programming flowchart (4 of 5) was irq caused by beginning of a break ? clear change-in- break status bit has end-of-break irq arrived yet ? clear change-in- break status bit remove break character from receiver fifo replace return address on system stack and monitor warm start address rte sirqr n y n does channel a receiver have a character ? place character in d0 n y abrki1 abrki y inch return sirq
serial module 8-36 mc68307 user? manual motorola figure 8-9. serial mode programming flowchart (5 of 5) outch n y is transmitter ready ? send character to transmitter return
motorola mc68307 user? manual 9-1 section 9 ieee 1149.1 test access port the mc68307 includes dedicated user-accessible test logic that is fully compatible with the ieee 1149.1 standard test access port and boundary scan architecture . problems asso- ciated with testing high-density circuit boards have led to development of this standard under the sponsorship of the test technology committee of ieee and the joint test action group (jtag). the mc68307 implementation supports circuit-board test strategies based on this standard. the test logic includes a test access port (tap) consisting of five dedicated signal pins, a 16-state controller, an instruction register, and four test data registers. a boundary scan reg- ister links all device signal pins into a single shift register. the test logic, implemented using static logic design, is independent of the device system logic. the mc68307 implementation provides the following capabilities: 1. perform boundary scan operations to test circuit-board electrical continuity 2. sample the mc68307 system pins during operation and transparently shift out the result in the boundary scan register 3. bypass the mc68307 for a given circuit-board test by effectively reducing the bound- ary scan register to a single bit 4. disable the output drive to pins during circuit-board testing 5. drive output pins to stable levels note certain precautions must be observed to ensure that the ieee 1149.1 test logic does not interfere with non-test operation. see section 9.6 non-ieee 1149.1 operation for details. 9.1 overview note this description is not intended to be used without the support- ing ieee 1149.1 document. the discussion includes those items required by the standard and provides additional infor- mation specific to the mc68307 implementation. for internal details and applications of the standard, refer to the ieee 1149.1 document. an overview of the mc68307 implementation of ieee 1149.1 is shown in figure 9-1. the mc68307 implementation includes a 16-state controller, a 4-bit instruction register, and four thi d t t d ith f m k 4 0 4
ieee 1149.1 test access port 9-2 mc68307 user? manual motorola test registers (a 1-bit bypass register, a 117-bit boundary scan register, a 6-bit module mode register, and a 32-bit id register). this implementation includes a dedicated tap consisting of the following signals: tck ?est clock input to synchronize the test logic (with pulldown). tms ?est mode select input (with an internal pullup resistor) that is sampled on the rising edge of tck to sequence the tap controller's state machine. tdi ?est data input (with an internal pullup resistor) that is sampled on the rising edge of tck. tdo ?hree-state test data output that is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. no trst pin is provided since the tap pin is reset by an internal power-on reset circuit. figure 9-1. test access port block diagram 4-bit instruction register tap ctlr t ms tck boundary scan register bypass tdi m u x m u x tdo test data registers (117 bits) 3 0 116 0 20 31 0 id = 1040201d mode id decoder
ieee 1149.1 test access port motorola mc68307 user? manual 9-3 9.2 tap controller the tap controller is responsible for interpreting the sequence of logical values on the tms signal. it is a synchronous state machine that controls the operation of the jtag logic. the state machine is shown in figure 9-2; the value shown adjacent to each arc represents the value of the tms signal sampled on the rising edge of the tck signal. for a description of the tap controller states, please refer to the ieee 1149.1 document. figure 9-2. tap controller state machine test logic reset run-test/idle select-dr_scan capture-dr select-ir_scan capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr update-dr exit2-ir update -ir 1 0 1 1 0 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 0 0 1
ieee 1149.1 test access port 9-4 mc68307 user? manual motorola 9.3 boundary scan register the mc68307 ieee 1149.1 implementation has a 124-bit boundary scan register. this reg- ister contains bits for all device signal and clock pins and associated control signals. the xtal, extal and rstin pins are associated with analog signals and are not included in the boundary scan register. all mc68307 bidirectional pins, except the open-drain i/o pins (halt , dtack , reset , scl and sda), have a register bit for the output path and another for the input path. in addi- tion, scl and sda have a third bit which controls these pins. all open drain i/o pins have a single register bit for pin data and no associated control bit. to ensure proper operation, the open-drain pins require external pullups. thirty-two control bits in the boundary scan register define the output enable signal for associated groups of bidirectional and three-state pins. the control bits and their bit positions are listed in table 9-1. boundary scan bit definitions are shown in table 9-2. the first column in table 9-2 defines the bit's ordinal position in the boundary scan register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted out is bit 116. the second column references one of the five mc68307 cell types depicted in figure 9-3 to figure 9-7, which describe the cell structure for each type. the third column lists the pin name for all pin-related bits or defines the name of bidirectional control register bits. the last column indicates the associated boundary scan register control bit. bidirectional pins include a single scan bit for data (io.cell) as depicted in figure 9-7. these bits are controlled by one of the two bits shown in figure 9-5 and figure 9-6. the value of the control bit determines whether the bidirectional pin is an input or an output. one or more bidirectional data bits can be serially connected to a control bit as shown in figure 9-8. note that, when sampling the bidirectional data bits, the bit data can be interpreted only after examining the io control bit to determine pin direction. table 9-1. boundary scan control bits name bit number name bit number name bit number name bit number bus.ctl 3 pa3.ctl 57 pb11.ctl 73 pb3.ctl 89 rw.ctl 10 pa2.ctl 59 pb10.ctl 75 pb2.ctl 91 adb.ctl 21 pa1.ctl 61 pb9.ctl 77 pb1.pu 93 ab.ctl 46 pa0.ctl 63 pb8.ctl 79 pb1.ctl 94 pa7.ctl 49 pb15.ctl 65 pb7.ctl 81 pb0.pu 96 pa6.ctl 51 pb14.ctl 67 pb6.ctl 83 pb0.ctl 97 pa5.ctl 53 pb13.ctl 69 pb5.ctl 85 dhi.ctl 99 pa4.ctl 55 pb12.ctl 71 pb4.ctl 87 dlo.ctl 108
ieee 1149.1 test access port motorola mc68307 user? manual 9-5 table 9-2. boundary scan bit definitions bit num cell type signal control bit num cell type signal control 0 o.cell ale pb0.pu 45 io.cell a22 ab.ctl 1 o.cell rd pb0.ctl 46 en.cell ab.ctl 2 o.cell wr scl 47 io.cell a23 ab.ctl 3 en.cell bus.ctl dhi.ctl 48 i.cell irq7 4 io.cell as d15 49 en.cell pa7.ctl 5 io.cell uds d14 50 io.cell bgack pa7.ctl 6 io.cell lds d13 51 en.cell pa6.ctl 7 io.cell rw d12 52 io.cell bg pa6.ctl 8 o.cell dtack d11 53 en.cell pa5.ctl 9 i.cell dtack d10 54 io.cell br pa5.ctl 10 en.cell rw.ctl d9 55 en.cell pa4.ctl 11 o.cell halt d8 56 io.cell tout2 pa4.ctl 12 i.cell halt dlo.ctl 57 en.cell pa3.ctl 13 o.cell reset d7 58 io.cell tout1 pa3.ctl 14 i.cell reset d6 59 en.cell pa2.ctl 15 o.cell cs0 d5 60 io.cell cs2d pa2.ctl 16 o.cell cs1 d4 61 en.cell pa1.ctl 17 o.cell cs2 d3 62 io.cell cs2c pa1.ctl 18 o.cell cs3 d2 63 en.cell pa0.ctl 19 o.cell clkout d1 64 io.cell cs2b pa0.ctl 20 i.cell busw d0 65 en.cell pb15.ctl 21 en.cell adb.ctl pb0.pu 66 io.cell int8 pb15.ctl 22 io.cell ad0 pb0.ctl 67 en.cell pb14.ctl 23 io.cell ad1 scl 68 io.cell int7 pb14.ctl 24 io.cell ad2 dhi.ctl 69 en.cell pb13.ctl 25 io.cell ad3 d15 70 io.cell int6 pb13.ctl 26 io.cell ad4 d14 71 en.cell pb12.ctl 27 io.cell ad5 d13 72 io.cell int5 pb12.ctl 28 io.cell ad6 d12 73 en.cell pb11.ctl 29 io.cell ad7 d11 74 io.cell int4 pb11.ctl 30 io.cell a8 d10 75 en.cell pb10.ctl 31 io.cell a9 d9 76 io.cell int3 pb10.ctl 32 io.cell a10 d8 77 en.cell pb9.ctl 33 io.cell a11 dlo.ctl 78 io.cell int2 pb9.ctl 34 io.cell a12 ab.ctl 79 en.cell pb8.ctl 35 io.cell a12 ab.ctl 80 io.cell int1 pb8.ctl 36 io.cell a13 ab.ctl 81 en.cell pb7.ctl 37 io.cell a14 ab.ctl 82 io.cell tin2 pb7.ctl 38 io.cell a15 ab.ctl 83 en.cell pb6.ctl 39 io.cell a16 ab.ctl 84 io.cell tin1 pb6.ctl 40 io.cell a17 ab.ctl 85 en.cell pb5.ctl 41 io.cell a18 ab.ctl 86 io.cell cts pb5.ctl 42 io.cell a19 ab.ctl 87 en.cell pb4.ctl 43 io.cell a20 ab.ctl 88 io.cell rts pb4.ctl 44 io.cell a21 ab.ctl 89 en.cell pb3.ctl 90 io.cell rxd pb3.ctl 104 io.cell d11 dhi.ctl
ieee 1149.1 test access port 9-6 mc68307 user? manual motorola 91 en.cell pb2.ctl 105 io.cell d10 dhi.ctl 92 io.cell txd pb2.ctl 106 io.cell d9 dhi.ctl 93 en.cell pb1.pu 107 io.cell d8 dhi.ctl 94 en.cell pb1.ctl 108 en.cell dlo.ctl 95 io.cell sda pb1.ctl/ pb1.pu 109 io.cell d7 dlo.ctl 96 en.cell pb0.pu 110 io.cell d6 dlo.ctl 97 en.cell pb0.ctl 111 io.cell d5 dlo.ctl 98 io.cell scl pb0.ctl/ pb0.pu 112 io.cell d4 dlo.ctl 99 en.cell dhi.ctl 113 io.cell d3 dlo.ctl 100 io.cell d15 dhi.ctl 114 io.cell d2 dlo.ctl 101 io.cell d14 dhi.ctl 115 io.cell d1 dlo.ctl 102 io.cell d13 dhi.ctl 116 io.cell d0 dlo.ctl 103 io.cell d12 dhi.ctl figure 9-3. output cell (o.cell) table 9-2. boundary scan bit definitions (continued) 1 mux 1 g1 1 mux 1 g1 from last cell 1 d c1 clock dr 1 d c1 update dr shift dr to next cell to output buffer 1 ?extest 0 ?otherwise data from system logic
ieee 1149.1 test access port motorola mc68307 user? manual 9-7 figure 9-4. input cell (i.cell) figure 9-5. output control cell (en.cell) from last cell 1 mux 1 g1 to device logic input pin shift dr clock dr 1d c1 to next cell 1 mux 1 g1 1 mux 1 g1 output control from system logic from last cell 1d c1 clock dr 1d c1 update dr to next cell to output enable 1 ?extest 0 ?otherwise shift dr
ieee 1149.1 test access port 9-8 mc68307 user? manual motorola figure 9-6. bidirectional cell (io.cell) figure 9-7. bidirectional cell (iox0.cell) 1 mux 1 g1 1 mux 1 g1 output from system logic from last cell 1d c1 clock dr 1d c1 update dr to next cell to output driver 1 ?extest 0 ?otherwise shift dr from pin input to system logic 1 mux 1 g1 1 mux 1 g1 output from system logic from previous cell 1d c1 clock dr 1d c1 update dr to next cell to output driver 1 ?extest 0 ?otherwise shift dr from pin input to system logic
ieee 1149.1 test access port motorola mc68307 user? manual 9-9 9.4 instruction register the mc68307 ieee 1149.1 implementation includes the three mandatory public instructions (extest, sample/preload, and bypass), the optional public id instruction, plus two additional public instructions (clamp and hi-z) defined by ieee 1149.1. the mc68307 includes a 4-bit instruction register without parity, consisting of a shift register with four par- allel outputs. data is transferred from the shift register to the parallel outputs during the update-ir controller state. the four bits are used to decode the seven unique instructions listed in table 9-3. the parallel output of the instruction register is reset to 0001 in the test-logic-reset controller state. note that this preset state is equivalent to the id instruction. figure 9-8. general arrangement for bidirectional pins table 9-3. instructions code instruction b3 b2 b1 b0 0000 extest 0001 id 0010 sample 1001 hi-z 1100 clamp 1101 module mode 1111 bypass io.cell en from last cell output data input data output enable i/o pin to next cell * note: more than one lo.cell could be serially connected and controlled by a single en.cell. en.cell *
ieee 1149.1 test access port 9-10 mc68307 user? manual motorola during the capture-ir controller state, the parallel inputs to the instruction shift register are loaded with the 4-bit binary value (0001). the parallel outputs, however, remain unchanged by this action since an update-ir signal is required to modify them. 9.4.1 extest (0000) the external test (extest) instruction selects the 117-bit boundary scan register. extest asserts internal reset for the mc68307 system logic to force a predictable benign internal state while performing external boundary scan operations. by using the tap, the register is capable of a) scanning user-defined values into the output buffers, b) capturing values presented to input pins, c) controlling the direction of bidirec- tional pins, and d) controlling the output drive of three-state output pins. for more details on the function and uses of extest, please refer to the ieee 1149.1 document. 9.4.2 sample/preload (0010) the sample/preload instruction selects the 117-bit boundary scan register and pro- vides two separate functions. first, it provides a means to obtain a snapshot of system data and control signals. the snapshot occurs on the rising edge of tck in the capture-dr con- troller state. the data can be observed by shifting it transparently through the boundary scan register. note since there is no internal synchronization between the ieee 1149.1 clock (tck) and the system clock (clkout), the user must provide some form of external synchronization to achieve meaningful results. the second function of sample/preload is to initialize the boundary scan register output bits prior to selection of extest. this initialization ensures that known data appears on the outputs when entering the extest instruction. 9.4.3 bypass (1111) the bypass instruction selects the single-bit bypass register as shown in figure 9-9. this creates a shift-register path from tdi to the bypass register and, finally, to tdo, circumvent- ing the 117-bit boundary scan register. this instruction is used to enhance test efficiency when a component other than the mc68307 becomes the device under test. figure 9-9. bypass register 1 mux 1 g1 1 d c1 clock dr f rom tdi 0 shift dr to tdo
ieee 1149.1 test access port motorola mc68307 user? manual 9-11 when the bypass register is selected by the current instruction, the shift-register stage is set to a logic zero on the rising edge of tck in the capture-dr controller state. therefore, the first bit to be shifted out after selecting the bypass register is always a logic zero. 9.4.4 clamp (1100) when the clamp instruction is invoked, the boundary scan multiplexer control signal extest is asserted, and the bypass register is selected. clamp should be invoked after valid data has been shifted into the boundary scan register, e.g., by sample/preload. clamp allows static levels to be presented at the mc68307 output and bidirectional pins, like extest, but without the shift latency of the boundary scan register from tdi to tdo. 9.5 mc68307 restrictions the control afforded by the output enable signals using the boundary scan register and the extest instruction requires a compatible circuit-board test environment to avoid device- destructive configurations. the user must avoid situations in which the mc68307 output drivers are enabled into actively driven networks. overdriving the tdo driver when it is active is not recommended. 9.6 non-ieee 1149.1 operation in non-ieee 1149.1 operation, the ieee 1149.1 test logic must be kept transparent to the system logic by forcing the tap controller into the test-logic-reset state. this requires the tms, tck and tdi inouts to be high.
motorola mc68307 user? manual 10-1 section 10 applications information 10.1 mc68307 minimum stand-alone system hardware this section details a simple stand-alone system using the mc68307. it demonstrates the simplicity of system hardware design and inherent low system chip count when using the highly integrated mc68307. the system hardware is shown in figure 10-1. the 5-v design consists of a 16.67mhz mc68307, 8-bit boot eprom, 16-bit sram, an rs232 driver and a few logic gates. it is considered stand-alone in that a dumb terminal (or terminal emulator) can be serially connected to the uart (via rs232) and used to control the system. 10.1.1 mc68307 signal configuration busw0 is tied low, meaning that the mc68307 boots up in 8-bit mode after reset. alterna- tively, busw0 could use a pull-up resistor to select 16-bit mode at reset, requiring a further 8-bit or a more expensive 16-bit eprom. clock crystal connection is simple. figure 10-1 shows a typical configuration. the usual oscillator start-up capacitors and bias resistor are included on-chip. the crystal parameters do not need to be particular values; c o (shunt capacitance) < 10pf and rx = 50 ohms were used in this case. an oscillator module could be used if preferred, connected to the extal pin with xtal unconnected. clkout is typically used as the reference clock for external system peripherals. in this case it remains unconnected. the rstin input can be used to extend the power-on reset time if desired. if slower system peripherals require an extended reset at power-up, an rc network attached to rstin can be used. in this case, the standard 32k clock stretch time at power-on suffices. at 16.67mhz, the 32k clocks equate to a 2ms reset hold-on interval allowing the clock and power supply to normalize. rstin is attached to a debounced button to cold reset the mc68307 (and the system if other devices are connected to the reset output). on each reset button press, the device is held in reset for the same 32k clocks as power-on. reset and halt are bidirectional open drain lines, requiring low value pull-up resistors to maintain the inactive state when not asserted. reset and halt are not used here, but could be asserted together to reset the system hardware if required. in this case the reset is not lengthened internally by 32k clocks. thi d t t d ith f m k 4 0 4
applications information 10-2 mc68307 user? manual motorola irq7 is used as a non-maskable software abort interrupt source, driven by a debounced abort button. whenever the button is pressed, a level 7 interrupt is asserted to the mc68307. at the next instruction boundary the interrupt request is acknowledged, with the mc68307 generating the corresponding interrupt vector. in fact, the mc68307 always supplies all its own interrupt vectors, whether the interrupt request is generated internally (by on-chip mod- ules), or externally (irq7 , int8 ?nt1 ). therefore, the interrupt vector numbers should be set up in the mc68307? pivr to point to the appropriate vector location in memory. dtack is a bidirectional open drain line used to terminate bus accesses. in this design, dtack is generated internally and asserted as an output using the mc68307? internal chip select and wait state control. external decode may also assert dtack as an input. as , uds , lds , and r/w control signals are all outputs. as the main asynchronous bus con- trols, each line has a pull-up resistor such that they are in the inactive state when they are not actively driven. they are not driven during reset, arbitration or cpu stop periods. chip select outputs (cs0 , cs1 , cs2 and cs3 ) are always driven and do not need pull-up resistors. the 8051-compatible control lines (ale, rd , wr ) are all unused outputs. the jtag input lines (tdi, tms, tck) are not used, so are pulled inactive through resistors. the tdo output is not connected. port a and port b signals default to general purpose inputs after reset. if they are to remain unconnected, they should be reprogrammed as outputs. otherwise pull-up resistors are necessary to ensure known input logic levels. all the port lines except pb2?b5 remain unconnected and are reprogrammed as outputs. port lines pb2?b5 are used in their ded- icated uart function. the txd and rts output lines use pull-up resistors to ensure logic levels between booting-up as a general purpose input and reprogramming as a uart out- put. a23 uses a pull-up resistor to select normal mc68307 processor mode at power-up. if instead it is pulled low through a resistor, a slave mode is selected. do not connect a23 to a supply rail directly. always use a pull-up/pull-down resistor. address/data/control buses are three-stated when the mc68307 is arbitrated off the bus, held in reset, or the cpu is stopped (via lpen bit in scr). if the buses are to be three-stated for an extended period of time, pull-up resistors are recommended for these lines. the pull- up resistor value is typically in the range 20k to 50k ohms, subject to leakage current and loading requirements.
applications information motorola mc68307 user? manual 10-3 figure 10-1. mc68307 minimum system configuration (1 of 2) as uds lds r/w a23 a22?0 d15?0 cs0 cs1 pa0?a7 pb0?b1 pb2/txd pb3/rxd pb4/rts rstin clkout extal xtal irq7 dtack halt reset busw0 tms tdi tck pb5/cts pb6?b15 5v 33k tdo ale rd wr 10k 10k 4k7 2k2 4k7 5v 5v 16.67 mhz 5v 10 m f 5v 33k 5v 33k 5v 33k 10 m f + + 5v 10 m f + + 10 m f tx rx rts cts to rs232 connector tx3 rx3 tx2 rx2 tx1 rx1 vss c1 c1+ vcc vdd c2+ c2 gnd di3 do3 di2 do2 di1 do1 5v 33k 5v 33k 5v 33k 5v 33k connect and ram to eprom components mc145407 reset 5v 5v 10k 10k mc68307 abort 5v 5v 10k 10k 5v 5v 5v 1 2 3 17 11 12 13 14 15 16 20 19 18 4 10 9 8 7 6 5 5v 10k cs2 cs3
applications information 10-4 mc68307 user? manual motorola figure 10-1. mc68307 minimum system configuration (2 of 2) a0 a0 12 a1 a1 11 a2 a2 10 a3 a3 9 a4 a4 8 a5 a5 7 a6 a6 6 a7 a7 5 a8 a8 27 a9 a9 26 a10 a10 23 a11 a11 25 a12 a12 4 a13 a13 28 a14 a14 29 a15 a15 3 a16 a16 2 d0 d8 13 d1 d9 14 d2 d10 15 d3 d11 17 d4 d12 18 d5 d13 19 d6 d14 20 d7 d15 21 pgm 31 e 22 vpp 1 g 24 cs0 5v 5v 10k 128k x 8 eprom 27c010 a15 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 1 d0 d0 11 d1 d1 12 d2 d2 13 d3 d3 15 d4 d4 16 d5 d5 17 d6 d6 18 d7 d7 19 e 20 w 27 g 24 32k x 8 static ram mcm6206 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 d0 d8 11 d1 d9 12 d2 d10 13 d3 d11 15 d4 d12 16 d5 d13 17 d6 d14 18 d7 d15 19 e 20 w 27 g 24 32k x 8 static ram mcm6206 r/w lds cs1 uds a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14
applications information motorola mc68307 user? manual 10-5 10.1.2 eprom memory interface the busw0 signal is used to select either an 8- or 16-bit eprom mode for boot-up after reset. in this case busw0 is tied low, and a standard, low cost, 8-bit eprom is used. the eprom interface is a straight connection of cs0 , address and data. the 8 data lines are connected on the upper half of the data bus (d15?8). cs0 is used to select the eprom and enable its output for a specified address range. after reset, the default cs0 programming is for the first 8 kbytes address range, accessible with 6 wait states. the cs0 registers are usually reprogrammed as one of the first software activ- ities, to set up the desired address space and wait state options. some processor systems need a read/write control signal to the eprom output enable to avoid data contention in the event of an accidental write to rom. the mc68307 can avoid this by programming cs0 to assert for read accesses only. note that with busw0 pulled high, the 16-bit eprom interface using two 8-bit eproms is equally simple. both eproms are chip selected by cs0 . the upper (even) byte eprom is output enabled by uds , while the lower (odd) byte eprom is output enabled by lds . the address lines used by two 27c010? would be a17?1. 10.1.3 ram memory interface the 16-bit ram interface is controlled using cs1 , uds , lds , r/w , address and data. cs1 is used to select ram for read/write accesses within a programmed address range. it must be software configured before any ram accesses are possible. for example, stacking oper- ations such as interrupt or exception handling, and subroutine branches are not possible until cs1 is configured. in this instance, cs1 should be programmed as a 16-bit port, with suitable address range, address space and wait states. the uds /lds signals are used to qualify accesses to the upper/lower byte of the selected ram data word. the r/w dictates whether a ram read or write takes place. it simplifies the interface to output enable the rams each time they are chip selected. although, when using alternative rams, care should be taken that the rams do not drive data out when output enabled during a write. almost all rams including the mcm6206 can do this. note that for an 8-bit ram interface using an mc6206, cs1 could be connected to the chip enable, uds to the output enable, r/w to the read/write, a14?0 to the address lines and d15-d8 to the data bus. after reset, cs1 must be software configured for 8-bit mode. 10.1.4 rs232 uart port the mc68307? uart signals (txd, rxd, rts , cts ) are connected to an mc145407 rs232 level driver. on the rs232 side, the uart signals are made available to a standard rs232 connector. this creates a communication channel between the user and system. for instance, a terminal (or terminal emulator) could control the system via a user preferred debug monitor coded into the eprom; this is an invaluable debug feature during the devel- opment stages of a system design.
applications information 10-6 mc68307 user? manual motorola 10.1.5 eprom timing the eprom interface offers zero wait state accesses with a 100ns eprom. a timing worth special note is the eprom enable to eprom data out time. cs0 is asserted on the rising edge of s2, and the selected eprom has to return valid data a setup time before the falling edge of s6 (an access time of approximately 2.5 clocks). at 5v and 16.67mhz, the equation for the eprom access time is as follows: 2.5 clocks ?data setup time ?clock to cs asserted time (maximum)= 150 ?5 ?30 = 115ns programming cs0 for 1 wait state would increase this access time to 175ns, while 6 wait states permit an access time up to 475ns at 16.67mhz, and 5v. for slow memories, the eprom chip enable high to output float time should be confirmed to ensure the eprom-driven data is removed before the start of the next bus cycle (next rising edge of s2). although the exact timing is dependent upon the system, a maximum time of 1 clock from cs0 negated to eprom data floating is a good guideline for use with the mc68307. 10.1.6 ram timing the r/w signal is always setup prior to the ram chip enable, so the timing is always ram enable (e) controlled rather than write (w) controlled. besides the additional delay intro- duced by the or gate for decoding the ram upper/lower byte enables, the ram read timing is the same as that of the eprom. it is the ram write timing that dictates the ram access time requirements. the ram chip enable to end of write time determines the necessary speed of ram. the chip enable time begins on the rising edge of s4 when the data strobes (uds , lds ) are asserted, and ends when the data strobes/cs1 negate, approximately 1 clock later. this typically includes rams with access times of up to 60?0ns, for zero wait states at 16.67mhz and 5v (check specific ram manufacturer? data sheets). the mcm6206s used have a 35ns access time. for proper timing of write cycles, it is also important to know how much time elapses between cs negated and the data output hold time. with a 5v, 16.67mhz mc68307, the data out hold time is a 15ns minimum. thus, on the enable controlled ram write cycle, the ram data-in hold time requirement must be 15ns or gate delay. when using a 74f32 or gate, the ram data-in hold time must be 7ns and while using a 74ac32 it must be 5ns. for the mcm6206, it is 0.
applications information motorola mc68307 user? manual 10-7 10.2 power management the fully static mc68307 has a number of flexible power management features that enable the power consumption to be minimized for different applications. this section describes how to use these features to best effect in reducing overall system power consumption. 10.2.1 fully static operation the mc68307 is fully static; this means that the clock to the device can be stopped com- pletely without causing damage. in addition the clock can be restarted with no loss of status occurring. these two fundamental benefits of fully static operation are utilized in the mc68307 power management features. the mc68307 allows the clocks to different modules within the device to be stopped under software control in order to minimize power consumption for a particular user application. the external clock input can also be varied in frequency between dc (i.e., stopped externally) and the maximum operating frequency (16.67 mhz). by setting the appropriate bits in the configuration register (mbcd, tmcd, uacd, ckd and lpen), the internal clocks to the m-bus, timer, uart, clkout and cpu can be individually stopped. with the exception of the cpu, these clocks can all be restarted by clearing the corresponding bit in the configuration register. when a module clock is turned off, the mod- ule current consumption is reduced to very low leakage levels. table 10-1 gives typical percentage power savings that can be made by stopping the clocks to modules that are not used in a particular operating mode. these figures are from mea- surements taken on a development board. they represent percentages of full operating power consumption and are averages over four different test cases (16.67mhz and 8mhz at 5v and 3.3v). table 10-1. power contribution from modules module percentage i dd all operational 100% clkout 5% m-bus 6% timer 7% uart 15% cpu (ec000) 61% low-power sleep 6%
applications information 10-8 mc68307 user? manual motorola 10.2.2 prescalable cpu clock it is apparent from table 10-1 that the ec000 cpu core contributes the most significant per- centage of the total power consumption. as well as being able to stop the clock to the cpu completely (when the cpu clock is stopped it cannot process code) this clock can be selec- tively programmed to a prescaled value. this is achieved by writing to the cden bit in the configuration register, with the cd2?d0 bits set to select the required prescale value. only the cpu clock is divided by this prescale value, the enabled clocks to the peripheral modules remain at the system clock frequency. hence the module interfaces will operate as normal. this mode of operation is useful when the cpu is required to do some background house- keeping tasks, which do not require the full processing power of the cpu, but one or more of the peripheral modules is required to be operating at full speed. the cpu can subse- quently select full speed clock by writing to the configuration register when an event occurs that requires the full processing power. the power consumption of the cpu is approximately proportional to the frequency, hence by carefully selecting the correct prescale value for the current task, the power contribution of the cpu to the overall device can be minimized. 10.2.3 wake-up when the cpu clock has been stopped in low-power sleep mode it can only be restarted by a wake-up condition or a system reset. any event that causes an interrupt wakes-up the cpu. for an interrupt to occur, the corresponding module must be clocked and the interrupt priority level must be set to nonzero in the corresponding field of the interrupt control regis- ter. it is also possible to set a bit in the configuration register (uacw) that automatically restarts the clock to the uart when a falling edge is detected on the rxd line. any subsequent inter- rupt from the uart module wakes-up the cpu. this very flexible feature enables the cpu to wake-up in response to many different events, for example: ?f uart receives a character ?f m-bus activity is detected ?fter a fixed time by programming a timer ?f an external interrupt occurs because there is no loss of data in the fully static cpu core, the wake-up latency is reduced to the minimum of only 10 system clocks. when the cpu wakes-up it immediately processes the interrupt and then returns to the mainline code from which it stopped its own clock. a stop instruction is not absolutely necessary when the mc68307 is put into low-power sleep mode, although, if such an instruction is used it will be handled correctly by the cpu. care must be taken with the interrupt mask since any interrupt wakes-up the cpu, but only interrupts of priority greater than the mask cause the cpu to exit from the sleep instruction.
applications information motorola mc68307 user? manual 10-9 the wake-up latency is increased slightly to 24 system clocks when a stop instruction is used. note that the mc68307 does not execute the lpstop instruction used by some other motorola microprocessors (for example, mc68060, mc68340, and mc68360). all enabled interrupts wake-up the cpu. if the interrupt mask in the cpu is set to a level greater than the active interrupt, this interrupt will not be processed immediately by the cpu. this technique gives the absolute minimum wake-up latency, since time-critical code can be placed immediately after the instruction that stopped the cpu clock, but before the interrupt mask is lowered to process the interrupt which caused the wake-up. the mc68307 does not require or generate a reset on wake-up. if the mc68307 is reset the cpu clock and all the other internal clocks are restarted, however the wake-up latency will be large since reset exception processing is required. 10.2.4 low-power sleep mode when all the internal clocks are stopped, including the cpu, the mc68307 is said to be in low-power sleep mode. in low-power sleep mode the external clock, either crystal oscillator or square wave input, is still toggling. the only logic internal to the mc68307 that is getting clocked is the reset circuit and interrupt controller. the device can wake-up from low-power sleep mode by an external interrupt on irq7 or any of the intx inputs. in addition the uart clock can automatically restart when a falling edge is detected on rxd, and subsequently wake-up the cpu when an interrupt occurs. the cpu is arbitrated off the system bus when it enters low-power sleep mode. the address and data buses are three-stated. for a system that has the mc68307 in this mode for pro- longed periods of time, the system address and data buses should be pulled up using high value resistors (e.g., 22?00kohms depending upon signal loading) to prevent these buses floating to mid-range voltage levels and hence generating large currents in input buffers. when a crystal is connected across extal and xtal pins on the mc68307 the contribution of the oscillator cell to the sleep-mode current is large. depending on the type of crystal used, this bias current can be up to several milliamps. careful choice of crystal and board layout can help minimize the effect of the bias current, but it will always make a significant contribution to sleep current. if an external oscillator is used to generate a square wave input to extal, the bias current is much less. when an external oscillator is used, the xtal pin should be left completely unconnected. low-power sleep mode consumes about 4% to 6% of the fully operational power depending on the configuration of the oscillator pins. 10.2.5 low-power stop mode the power consumption of the mc68307 can be minimized by stopping the clock to the extal pin externally. this is referred to as low-power stop mode. external hardware is required to control the system clock circuit. the current consumption of the mc68307 is at an absolute minimum in this mode.
applications information 10-10 mc68307 user? manual motorola note that since the external clock input to the mc68307 is stopped the device cannot wake- up from low-power stop mode directly. because the mc68307 is fully static, the clock can be stopped at any time and in any phase. lowest power will be obtained if the clock is stopped after the device has been put into low- power sleep mode. if the clock is stopped when the cpu is executing a bus cycle or pro- cessing an instruction the current will not be minimal. low-power sleep mode uses arbitra- tion to ensure that the cpu is idle before stopping the internal clock. when the clock is restarted, the mc68307 will continue processing from where it was previ- ously with no loss of status. if the device is in low-power sleep mode an interrupt will be required to wake-up the cpu. instead of stopping the clock externally the frequency could be reduced to a very low value in order to minimize power. the whole mc68307 could operate at this reduced frequency, allowing timers for example to wake-up the cpu after a long delay and subsequently set a general purpose port line to reselect the maximal frequency external clock. whenever the external clock is being stopped, started or multiplexed, care must be taken to ensure that no pulses narrower than the specified minimum clock high or low periods are generated (minimum pulse width = 27 ns). if an external crystal is stopped then started again there may be considerable wake-up latency due to the crystal start-up time. this depends on the external component selection and is not a function of the mc68307. 10.3 using m-bus software to communicate between processor systems m-bus is an i 2 c-compatible bus interface used in the mc68300 family. it is a serial interface comprising two open drain bidirectional signals, namely serial clock (scl) and serial data (sda). multiple devices can be connected directly to these open drain lines, and indeed this is good reason for the widespread adoption of the bus as an efficient ic communication method in end-systems. a typical scenario would consist of a processor with an m-bus master controlling the data flow between several slaves, such as lcds, real-time clocks, keypads, a/d converters and memories. moreover, a built-in bus collision mechanism supports multiple m-bus masters as well as multiple slaves. the m-bus module of the mc68300 is flexible enough to operate as either an m-bus master or a slave. this section demonstrates control software for m-bus communication between two identical mc68307 systems, one configured with an m-bus master and the other an m-bus slave. only a short piece of initialization code must be changed to make the mc68307 code appli- cable to other mc68300 devices with m-bus.
applications information motorola mc68307 user? manual 10-11 10.3.1 overview of m-bus software transfer mechanism for clarity, a brief overview of the m-bus software control mechanism is provided here. the m-bus communication is on a byte-wide basis. the components of the hardware trans- fer protocol are a start condition, 8 data bits, an acknowledge bit and a stop condition. before starting a communication, an m-bus master should carry out a software check to ensure the bus is free, and therefore all other m-bus transfers are complete. thereafter, the bus master initiates a transfer by software, writing a start condition onto the bus. this is an indicator to all connected m-bus devices that the master is taking charge of the bus and that the address of the targeted slave is to follow. for the mc68300 m-bus master, writing the targeted slave address to the data register initiates the 8-bit transfer (msb first). if a system has two or more m-bus masters which poll the bus free and start a transfer at the same time, then the collision detection arbitration throughout the transfer of the slave address transfer and subsequent data bytes decides which device gets charge of the bus. if the mc68300 m-bus loses arbitration in this way, it stops driving data onto the bus to pre- vent data corruption. furthermore, it switches automatically into slave mode, pre-empting the alternate master addressing it as a slave. if interrupts are enabled, an interrupt is gen- erated on the completion of that byte, and a status bit indicates arbitration lost as the inter- rupt source. the first data byte transmitted by the m-bus master is always the targeted slave address, with the least significant bit determining whether the slave remains ready to receive or trans- mit subsequent bytes. the addressed slave can then acknowledge the received byte, or not, depending upon the software protocol and acknowledge capability of the slave devices used. each acknowledge is like a 9th data bit, asserted by the receiver as a handshake to successfully transmitted data. a block transfer comprising a series of data bytes (and acknowledge bits) follows as com- manded by the software protocol. the bus remains busy throughout the block, precluding all other masters from starting transfers. at the end of the block, the bus master relinquishes the bus by software placing a stop condition onto the bus. ultimately, the m-bus master is responsible for starting and stopping transfers, but the num- ber of bytes transferred can be dictated by either the master or slave depending upon the desired software protocol. for example, a slave may acknowledge all bytes received until it saturates, at which point the master stops the block transfer. alternatively, the slave receiver may acknowledge received bytes until the master transmitter indiates that there are no more bytes to send. indeed, both master and slave can be charged with controlling the transfer block. for instance, the software protocol may transfer a byte count as part of the communication or use a fixed number of transfer bytes every time. for the best choice in software control, transfers can adopt either a status polling method or interrupts at the end of each byte. the interrupt option is most commonly used to minimize the processor overhead or the time during which the processor is tied up with the transfers. if enabled, the interrupts are generated on the completion of each 9 bits (8 data bits plus an acknowledge).
applications information 10-12 mc68307 user? manual motorola 10.3.2 m-bus master mode operation using interrupts to transmit data to the addressed slave is straight forward. during the m- bus initialization, the mc68300 m-bus sets up the master transmitter mode, sets the m-bus frequency, enables interrupts, provides an interrupt handler and starts the block transfer. the targeted slave address (with lsb = 1 for slave receiver mode) is transmitted by writing to the m-bus data register. on each subsequent end-of-byte interrupt, further data bytes are transmitted by writing data to the m-bus data register until the block is complete. on the interrupt at the end of the last byte the software stops the transfer. for receiving from the addressed slave, the initialization is exactly the same. remember that even if receiving, the first operation is to transmit the targeted slave address (except that this time lsb = '0'). in the interrupt handler at the end of the slave address transmit byte, the transmit mode is changed to receive. then, to initiate the first byte receive operation, the mc68300 m-bus master software carries out a dummy read of the data register. no sensible data is read at this point, but it is the action of this read which starts the data receive. at the end of each subsequent received byte, the interrupt generated is used to read the data reg- ister again for valid data, and to start the next byte receive. this continues until the master receiver stops the block transfer. the receiver is always responsible for the generation of acknowledges. the mc68300 m- bus receiver can be programmed to generate acknowledges automatically for each byte received. most slave transmitters take an acknowledge from the master receiver to mean that further bytes are desired. in fact, for some slave transmitters it is necessary for the mas- ter receiver to acknowledge all received bytes except the last one, to indicate that more data byte transmits are required. this is not a requirement of the mc68300 m-bus slave. 10.3.3 m-bus slave mode operation many of the principles discussed for the master operation also hold true for the slave mc68300 m-bus. the main differences are that the mc68300 slave m-bus is not controlling the transfer (starting and stopping) or providing the m-bus clock, but is instead following what the master dictates. for slave operation, again initialize the m-bus frequency, m-bus slave address, interrupt handler and interrupt enable. as the first transfer is always the receipt of the slave address, slave receive mode should always be programmed initially. all target slave addresses which are transmitted by the master (first byte after start) are then checked against the pro- grammed mc68300 m-bus slave address for a match. when they match, the mc68300 m- bus slave generates an interrupt (if enabled), and a status bit indicates the cause as m-bus addressed-as-slave (maas). on entering the corresponding interrupt handler, the software read/write status indicator is read to determine whether the slave is to receive or transmit subsequent bytes and that the transmit/receive mode is set accordingly. if in transmit mode, the first data byte transmit is initiated by writing to the data register. if in receive mode, the first receive byte is initiated by a dummy read of the data register. there is no sensible data read at this point, but having started the receive process, data register reads in subsequent end-of-byte interrupts obtain
applications information motorola mc68307 user? manual 10-13 valid data and initiate the next byte receive. again, the software protocol between m-bus master and slave determines the use of acknowledges. 10.3.4 description of setup the hardware consists of two identical mc68307 systems connected together via the m-bus as shown in figure 10-2. both systems have the mc68307 processor core executing instructions prefetched from its own rom. figure 10-2. hardware setup each mc68307 system has 128 kbytes eprom and 128 kbytes sram and runs a debug monitor. a complete description of the system hardware is provided in an490, titled ?ultiple bus interfaces using the mc68307. using the monitor's download facility, an m-bus control program is downloaded into the sram of each board. the code allows one system to control its m-bus module as a master, while the other implements an m-bus slave. together, the two software programs allow the mc68307 m-bus master to write data to the mc68307 m-bus slave and later read it back for verification. 10.3.5 software flow the mc68307 master m-bus controls the number of blocks transferred via start and stop conditions. in this example, there are only two communication blocks, one transmit- ting data to the slave (master transmit block), and one receiving data back from the slave for verification (master receive block). the master/slave responsibilities during the master transmit block are outlined in figure 10-3 and for the master receive block in figure 10-5. on these diagrams, note that for a given transfer byte, the end-of-byte interrupts on the mas- ter and slave occur at around the same time. the built-in m-bus transfer mechanism means it does not matter in which order they are serviced. the master and slave interrupt service order used in the flowcharts of figure 10-3 and figure 10-5 is purely for demonstration pur- poses. the interrupt handlers are shown such that the data flow is always from transmitter to receiver, although, it should be understood that the master and slave interrupt handlers are happening at the same time, as are the transmit and receive of a particular byte between the two systems. mc68307 system scl sda master m-bus mc68307 system scl sda slave m-bus 5v 2.2k 2.2k
applications information 10-14 mc68307 user? manual motorola 10.3.6 transfer blocks the master m-bus controls of the number of data bytes within each transmit/receive block. observe figure 10-4 and figure 10-6, which give a summary of the activity on the m-bus during the master transmit and master receive blocks respectively. when the master is transmitting data (master transmit block) the slave acknowledges all bytes received, and the master decides when the transfer is completed by setting a stop condition (see figure 10-4). when the master is receiving data (master receive block) it decides when the transfer is complete by stopping acknowledges on the last received byte, thereby stopping the slave transmitting, and setting a stop condition (see figure 10-6). 10.3.7 software implementation the software used is shown in section 10.3.7.1 software listing 1?-bus master soft- ware and section 10.3.7.2 software listing 2?-bus slave software . only the method of enabling the m-bus and interrupts at the start of the software listings is specific to the mc68307. thereafter, the code is generic for any mc68300 device with an m-bus module. the mc68300 m-bus slave software should always be set running before the master soft- ware, such that the prospective slave is initialized as a receiver before the master transmits the slave address. the software uses interrupts to control the byte transfers within each block. the m-bus mas- ter starts the transfer by transmitting the slave address. thereafter interrupts are generated on both the master and slave m-bus to control the test. the m-bus hardware protocol does not care which order the interrupts are serviced by the master (transmitter or receiver) or slave (transmitter or receiver) at the end of each byte. consider that the master is in charge of generating the scl clocks to shift data out the transmitter and into the receiver, when a transmit/receive is initiated by writing/reading the m-bus data register respectively. how- ever, the clocks do not start until the slave has released the clock line on the bus by making its corresponding read/write of its m-bus data register. therefore, both mc68300 m-bus master and slave interrupts have to initiate the next data transfer. the slave frequency can be programmed as greater or less than that of the master. m-bus implements a clock synchronization mechanism such that the clock with the shortest high time and longest low time dictates the open drain clock. for example, if the programmed slave m-bus clock frequency is less than the master, the slave can stretch the clock as nec- essary. the number of transfer and receive blocks and the number of data bytes within each block can be altered in the master software. the slave software remains the same throughout. if the user desires detailed crosschecks on the software flow, interrupt counts (for number of bytes transferred) or a flag passing mechanisms could be implemented. for simplicity this is not used in the example software.
applications information motorola mc68307 user? manual 10-15 figure 10-3. master/slave responsibilities for the master transmit block figure 10-4. summary of m-bus activity for the master transmit block m-bus master transmitter activity m-bus slave receiver activity ?interrupt at end of address tx ?verify acknowledge ?remain in tx mode ?write 1st data byte (aa) to mbdr to initiate tx ?interrupt at end of 1st data byte tx ?verify acknowledge ?write 2nd data byte (55) to mbdr to initiate tx ?interrupt at end of 2nd data byte tx ?verify acknowledge ?stop block transfer ?set slave rx mode ?set master tx mode ?start block transfer ?write slave address to mbdr to initiate address tx (66) (slave is to rx data, so lsb = 0) ?tx slave address ?rx slave address ?auto?acknowledge address ?interrupt on slave address match ?set tx/rx mode to rx ?dummy read of mbdr, ready rx 1st data byte ?tx data ?rx data ?auto- acknowledge data ?interrupt at end of 1st data byte rx ?read 1st byte of valid data from mbdr (aa), and ready for next rx ?tx data ?rx data ?auto-acknowledge data ?interrupt at end of 2nd data byte rx ?read 2nd byte of valid data from mbdr (55), and ready for next rx master activity m-bus slave activity start 66 ack aa ack 55 ack stop start block tx slave address (slave to rx) rx slave address ack tx 1st data byte ack ack rx 1st data byte tx 2nd data byte rx 2nd data byte stop block
applications information 10-16 mc68307 user? manual motorola figure 10-5. master/slave responsibilities for the master receive block figure 10-6. summary of m-bus activity for the master receive block ?set master tx mode ?start block transfer ?write slave address to mbdr to initiate address tx (67) (slave to rx so lsb = 1) m-bus master receiver activity m-bus slave transmitter activity ?auto-acknowledge data ?interrupt at end of 1st data byte rx ?read of mbdr ready to rx 2nd data byte (55) ?no acknowledge ?interrupt at end of 2nd byte rx ?stop block transfer ?tx slave address ?rx slave address ?auto-acknowledge address ?interrupt on slave address match ?set tx/rx mode to tx ?write 1st data byte (aa) to mbdr ready to tx ?t x data ?interrupt at end of address tx ?verify acknowledge ?set tx/rx mode to rx ?dummy read of mbdr to initiate rx of 1st data byte (aa) ?rx data ?rx data ?tx data ?interrupt at end of 2nd data byte tx ?no acknowledge, so end tx ?switch to slave rx mode ready for next slave address ?set slave rx mode ?interrupt at end of 1st data byte tx ?verify acknowledge ?write 2nd data byte (aa) to mbdr to initiate tx master activity m-bus slave activity start 67 ack aa ack 55 no ack stop start block tx slave address (slave to tx) rx slave address ack rx 1st data byte no ack ack tx 1st data byte rx 2nd data byte tx 2nd data byte stop block
applications information motorola mc68307 user? manual 10-17 10.3.7.1 software listing 1?-bus master software * * motorola 68307 imbp test board - m-bus * * * module: mbm_int.src date: 8/4/94 * * developed by : motorola * hi-end applications * east kilbride. * * notes: * master m-bus routine using interrupts for a master/slave test * * the number of bytes transmitted and received is completely * controlled by the master. (i.e. when the slave is receiving data, * it acknowledges all the time, and the master dictates the number of * bytes to transfer. when the slave is transmitting, the master * receiver acknowledges dictate whether the slave is to send further * bytes or not. * * the master: * 1) writes out the slave chip address, and 2 slave data bytes. * 2) writes out the slave chip address, and reads 2 slave data bytes * 3) verifies the data read back against that originally sent. * * * external reference declarations * xref scr ; system control reg xref pbcnt ; port b control reg xref pivr ; peripheral interrupt vector reg xref picr ; peripheral interrupt control reg xref madr ; m-bus address reg xref mfdr ; m-bus freq divider reg xref mbcr ; m-bus control reg xref mbsr ; m-bus status reg xref mbdr ; m-bus data reg * * constants * uvecbase equ $100 ; user vector base mbusvec equ uvecbase+($d*4) ; m-bus vector location mbushan equ $15000 ; m-bus interrupt handler location s307_ad equ $66 ; slave 68307 m-bus address drxcnt equ $3 ; data receive count (2 + 1 dummy) atxcnt equ $1 ; address transmit count dtxcnt equ $2 ; data transmit count * * main program *
applications information 10-18 mc68307 user? manual motorola org $10000 ; random location for assembly and.l #$fffffeff,scr ; clear scr bit 8, m-bus clock active move.b #$40,pivr ; vector = #$40, vector @ address $100 or.w #$000d,picr ; m-bus interrupt level = 5 move.l #mbushan,mbusvec ; set up m-bus interrupt handler or.w #$0003,pbcnt ; enable m-bus lines bsr init_mbm ; initialize m-bus as master * write to slave 68307 m-bus * write chip address, and two bytes of data start bsr mbbusy ; poll the m-bus, wait till bus free move.b #0,v_drxcnt ; data receive count move.b #atxcnt,v_atxcnt ; address transmit count move.b #dtxcnt,v_dtxcnt ; data transmit count move.b #1,v_write ; set write to slave var = true move.b #s307_ad,v_chipad; slave 68307 m-bus receiver addr. move.l #s307_data,a0 ; pointer to stored data for transfer bsrwrite1 ; send out the chip address * read from slave 68307 m-bus * write chip address, and read two bytes of data bsr mbbusy ; poll the m-bus, wait till bus free move.b #drxcnt,v_drxcnt ; data receive count move.b #atxcnt,v_atxcnt ; address transmit count move.b #0,v_dtxcnt ; data transmit count move.b #0,v_write ; set write to slave var = false move.b #s307_ad,d6 ; alter chip address lsb for or.b #$01,d6 ; slave transmit and move.b d6,v_chipad ; write to chip address variable move.l #s307_data,a0 ; pointer to data for memory 1 bsr write1 ; send out the chip address *test complete bsr mbbusy ; poll the m-bus, wait till bus free forever bra forever ; test complete & passed, loop forever * * m-bus setup/initialization * init_mb mmove.w #$2700,sr ; disable interrupts ?set to level 7 move.b #0,mbsr ; clear interrupt pend, arbitr. lost move.b #$0c,mfdr ; set frequency move.b #$00,mbcr ; disable and reset m-bus move.b #$80,mbcr ; enable m-bus rts * note - by not writing madr, the 68307 m-bus slave address = 0 * * poll the m-bus busy *
applications information motorola mc68307 user? manual 10-19 mbbusy btst #5,mbsr ; test mbb bit, bne mbbusy ; and wait until it is clear rts * * generation first byte of data transfer * write1 btst #5,mbsr ; test mbb bit, bne write1 ; and wait until it is clear txstart bset #4,mbcr ; set transmit mode bset #5,mbcr ; set master mode (generate start) bset #6,mbcr ; enable m-bus interrupts move.w #$2000,sr ; enable interrupts ?set to level 0 mbfree btst #5,mbsr ; test mbb bit, beq mbfree ; if bus is still free, wait until busy rts * * post byte transmission/reception software response * org mbushan ; start of interrupt handler isr bclr #1,mbsr ; clear the mif flag move.l d0,-(a7) ; push d0 register to stack move.l d1,-(a7) ; push d1 register to stack move.l #0,d0 ; clear general data reg move.l #0,d1 ; clear general data reg btst #5,mbcr ; check the msta flag beq slave ; branch if slave mode btst #4,mbcr ; check the mode flag beq mastrx ; branch if receive mode * * master transmit caused interrupt * mastx btst #0,mbsr ; check ack from receiver, bne endmastx ; if no ack, end transmission txaddr move.b v_atxcnt,d1 ; check address tx count beq txdata ; if address complete go to data subq.b #1,v_atxcnt ; decrement address tx count txdata move.b v_write,d1 ; check if writing or reading slave beq setmastrx ; if reading set to master receive move.b v_dtxcnt,d1 ; check data tx count beq endmastx ; if no more data then stop bit subq.b #1,v_dtxcnt ; reduce tx count move.b (a0)+,mbdr ; transmit next byte bra end ; exit endmastx bclr #5,mbcr ; generate stop condition
applications information 10-20 mc68307 user? manual motorola bra end ; exit setmastrx bclr #3,mbcr ; enable txak bclr #4,mbcr ; set master receive mode bset #5,mbcr ; set master mode (generate start) * * master receive * mastrx subq.b #1,v_drxcnt ; decrement receive count move.b v_drxcnt,d1 cmp.b #drxcnt-1,d1 ; first byte read check bne notfirst ; if not first, read etc. as usual move.b mbdr,d0 ; if first, dummy read only to start rx bra end notfirst cmp.b #0,d1 beq enmasr ; last byte to be read check subq.b #1,d1 ; last second byte to be read check bne nxmar ; not last one or last second, so branch lamar bset #3,mbcr ; last second, disable ack transmitting bra nxmar enmasr bclr #5,mbcr ; last one, generate stop signal nxmar move.b mbdr,d0 ; read data cmp.b (a0)+,d0 ; compare with written data beq end ; if data as expected o.k. readerr bra readerr ; else error loop forever. end move.l (a7)+,d1 ; pop d1 register from stack move.l (a7)+,d0 ; pop d0 register from stack rte slave nop bra slave ; slave operation not implemented * * buffers and variables * v_write dc.b $1 ; slave write = true v_chipad dc.b s307_ad ; chip address variable = slave 307 add v_drxcnt dc.b drxcnt ; set up variables - data receive count v_atxcnt dc.b atxcnt ; - addr transmit count v_dtxcnt dc.b dtxcnt ; - data transmit count s307_data dc.b $aa,$55 ; chip 1 data end
applications information motorola mc68307 user? manual 10-21 10.3.7.2 software listing 2?-bus slave software * * motorola 68307 imbp test board - m-bus * * * module: mbm_int.src date: 8/4/94 * * developed by : motorola * hi-end applications * east kilbride. * * notes: * slave m-bus routine using interrupts for a master/slave test * * the number of bytes transmitted and received is completely * controlled by the master. (i.e. when the slave is receiving data, * it acknowledges all the time, and the master dictates the number of * bytes to transfer. when the slave is transmitting, the master * receiver acknowledges dictate whether the slave is to send further * bytes or not. * * the slave: * 1) recognizes its slave chip address, and receives 2 data bytes. * 2) recognizes its slave chip address, and transmits the 2 bytes * * external reference declarations * xref scr ; system control reg xref pbcnt ; port b control reg xref pivr ; peripheral interrupt vector reg xref picr ; peripheral interrupt control reg xref madr ; m-bus address reg xref mfdr ; m-bus freq divider reg xref mbcr ; m-bus control reg xref mbsr ; m-bus status reg xref mbdr ; m-bus data reg * * constants * uvecbase equ $100 ; user vector base mbusvec equ uvecbase+($d*4) ; m-bus vector location mbushan equ $15000 ; m-bus interrupt handler location s307_ad equ $66 ; slave 68307 m-bus address * * main program * org $10000 ; random location for assembly and.l #$fffffeff,scr ; clear scr bit 8, m-bus clock active move.b #$40,pivr ; vector = #$40, vector @ address $100 or.w #$000d,picr ; m-bus interrupt level = 5 move.l #mbushan,mbusvec ; set up m-bus interrupt handler
applications information 10-22 mc68307 user? manual motorola or.w #$0003,pbcnt ; enable m-bus lines bsr init_mbs ; initialize m-bus as slave finish bra finish ; loop forever * * m-bus setup/initialization * init_mbs move.w #$2700,sr ; disable interrupts ?set to level 7 move.b #0,mbsr ; clear interrupt pend, arbitr. lost move.b #$10,mfdr ; set frequency move.b #s307_ad,madr ; set m-bus slave address move.b #$00,mbcr ; disable and reset m-bus or.b #$c0,mbcr ; enable m-bus, ints, txak move.w #$2300,sr ; enable ints by setting to level 3 rts * * poll the m-bus busy * mbbusy btst #5,mbsr ; test mbb bit, bne mbbusy ; and wait until it is clear rts * * post byte transmission/reception software response * org mbushan ; start of interrupt handler isr bclr #1,mbsr ; clear the mif flag move.l d0,-(a7) ; push d0 register to stack move.l d1,-(a7) ; push d1 register to stack move.l #0,d0 ; clear general data reg move.l #0,d1 ; clear general data reg * interrupt counter addq.l #1,d3 ; (not used, simply monitor) btst #5,mbcr ; check the msta flag beq slave ; branch if slave mode master bra master ; master not implemented, so error * slave move.b mbsr,d6 ; read mbsr btst.b #6,d6 ; is it slave address byte? beq slave_data ; if not, then data * * addressed as slave * slave_add btst #2,d6 ; read srw to verify slave tx or rx beq init_srx ; if rx, initialize slave receive count init_stx or.b #$10,mbcr ; set transmit mode move.l #databuf,a0 ; pointer to data storage buffer move.b (a0)+,mbdr ; first data byte transmit
applications information motorola mc68307 user? manual 10-23 bra end_slave init_srx and.b #$e7,mbcr ; set receive mode and txak move.l #databuf,a0 ; pointer to data storage buffer move.b mbdr,d0 ; start receive via dummy byte read bra end_slave * * slave data * slave_data btst #4,mbcr ; read tx or rx mode beq srx_data * * post slave data transmit control * stx_data btst #0,mbsr ; check ack from receiver, beq nxt_tx ; if ack, then tx next data byte and.b #$ef,mbcr ; tx complete so swap to rx move.b mbdr,d0 ; dummy read to free bus (scl) bra end_slave ; finish and await master nxt_tx move.b (a0)+,mbdr ; tx next data byte bra end_slave ; exit * * post slave data receive control * srx_data move.b mbdr,d0 ; read data move.b d0,(a0)+ ; store data in next buffer location end_slave move.l (a7)+,d1 ; pop d1 register from stack move.l (a7)+,d0 ; pop d0 register from stack rte * * buffers and variables * databuf ds.b 0 ; slave data buffer between rx and tx end
applications information 10-24 mc68307 user? manual motorola 10.4 mc68307 uart driver examples the mc68307 uart driver code listed in this section was developed from mc68681 duart driver software. the two principal changes described below are (a) the implemen- tation of one uart channel, and (b) the use of the uart timer as the uart baud rate source. the uart driver code is given in section 10.4.1 software listing 3 . it provides well commented initialization, status, input and output routines. (a) where the duart implemented two serial channels, the mc68307 uart implements one. accordingly, the memory map has changed to include only those registers appropri- ate to the single channel (channel a). (b) for peak integration of the mc68307, all internal module clocks are based on the sin- gle processor clock. so, while the mc68681 based the standard baud rate settings of its clock select register on a fixed 3.6864mhz external clock source, the mc68307? baud rate is developed from its 16.67mhz to d.c. range processor clock source. therefore, the mc68307 uses its programmable uart timer to prescale this processor clock source, and generate the baud rate reference as desired. the equation to calculate the uart timer prescaler for a desired baud rate is: baud rate generator prescaler = 68307 clock frequency/[16 x 2 x (uart baud rate)] where, baud rate generator prescaler = {ubg1:ubg2} e.g., for 9600 baud from a 16.67mhz clock, the uart timer prescaler is 54 decimal (36 hex). so, ubg1 = 0x00 and ubg2 = 0x36. note the standard baud rate settings of the mc68307? uart clock select register (ucsr) are only relevant if the processor clock frequency is a suitable multiple of 3.6864 mhz. 10.4.1 software listing 3 sio equ $fff101 ; serial io base address * portw equ 1 ; byte wide port portw equ 2 ; word wide port * portw equ 4 ; long word wide port con_index equ 0 umr1 equ 0*portw ; mode register 1 umr2 equ 0*portw ; mode register 2 usr equ 1*portw ; status register ucsr equ 1*portw ; clock select register ucr equ 2*portw ; command register urb equ 3*portw ; receiver buffer register utb equ 3*portw ; transmitter buffer regiseter uacr equ 4*portw ; auxiliary control register
applications information motorola mc68307 user? manual 10-25 uisr equ 5*portw ; interrupt status register ubg1 equ 6*portw ; counter/timer upper register ubg2 equ 7*portw ; counter/timer lower register brgset1 equ 0 ; bit 7 selects set 1 if clear * crgset2 equ $e0 ; bit 7 selects set 2 if set ; timer mode, divided by 1 scaleu equ 0 ; upper byte prescaler for timer scalel equ 54 ; lower byte prescale for timer * con_sr equ sio+con_index+usr con_rh equ sio+con_index+urb con_cr equ sio+con_index+ucr con_th equ sio+con_index+utb brkrecd_bit equ 7 ; break received if set errframe_bit equ 6 ; framing error if set errpar_bit equ 5 ; parity error if set errover_bit equ 4 ; overrun error if set txemt_bit equ 3 ; transmitter empty if set txrdy_bit equ 2 ; transmitter ready ffull_bit equ 1 ; fifo full if set rxrdy_bit equ 0 ; receiver ready if set rstmrptr equ $10 ; reset mode register pointer rstrcvr equ $20 ; reset receiver rstxmit equ $30 ; reset transmitter rsterror equ $40 ; reset errors rstbrk equ $50 ; reset break change interrupt setbrk equ $60 ; start break endbrk equ $70 ; stop break distx equ $08 ; disable transmitter enatx equ $04 ; enable transmitter disrx equ $02 ; disable receiver enarx equ $01 ; enable receiver page * * init procedure (both ports) * input: none * output: none * con_init: movem.l d1/a0-a1,-(sp) ; save registers move.l #2000,d1 con_wait: btst.b #txemt_bit,con_sr; wait for xmtr to finish nop dbne d1,con_wait lea.l sio+con_index,a0 ; console port move.l #$001307dd,d1 ; no parity ; 8 data bits ; 1 stop bit ; timer for baud rate
applications information 10-26 mc68307 user? manual motorola bsr init ; init console movem.l (sp)+,d1/a0-a1 ; restore registers rts init: move.b #rstmrptr,ucr(a0); reset mode register move.b #crgset2,sio+uacr; set the baud rate set move.b #scaleu,sio+ubg1 ; set timer prescalar for 9600 baud move.b #scalel,sio+ubg2 ; move.b #0,uisr(a0) ; clear int status register rol.l #8,d1 rol.l #8,d1 move.b d1,umr1(a0) ; setup mode register 1 rol.l #8,d1 move.b d1,umr2(a0) ; setup mode register 2 rol.l #8,d1 move.b d1,ucsr(a0) ; set baud rate clock as timer move.b #rstrcvr,ucr(a0) ; reset the transmitter move.b #rstxmit,ucr(a0) ; reset the receiver move.b #enarx,ucr(a0) ; enable receiver rts page * * status procedure: * input: none * output: d0 = 0 if receive buffer empty * = 1 if receive buffer full * = 2 if break detected * con_sts: move.b con_sr,d0 ;read status register btst.b #rxrdy_bit,d0 beq con_sts_1 ; nothing yet btst.l #brkrecd_bit,d0 ; break? beq con_sts_1 ; no move.b con_rh,d0 ; read in break char move.b #rstbrk,con_cr ; req'd by 68681 move.b #rsterror,con_cr ; move.b #2,d0 ; break status rts con_sts_1: andi.b #1,d0 ; return 1 or 0 rts * * input procedure * input: none * output: d0 = character * this is called only after a status of 'buffer full' has been read * con_in: move.b con_rh,d0 move.b #rsterror,con_cr ; rts
applications information motorola mc68307 user? manual 10-27 page * * output procedure * input: d0.b = character * output: none * caller assumes character is 'logically' written after this call * con_out: move.b #enatx,con_cr ;enable transmitter con_out_1: btst.b #txrdy_bit,con_sr;wait until beq.s con_out_1 ;transmitter ready move.b d0,con_th ;send char rts end 10.5 swapping rom and ram mapping on the mc68307 it is often essential for embedded systems to locate the exception and interrupt vectors in read/write memory, to allow vector table changes after system boot-up. indeed, before being able to port some debug monitors to an application this is a requirement. for cpu32 based mc68300 integrated processors, the vector base register (vbr) resolves this issue, permitting vectors to be located anywhere in the address space. for mc68300 processors with an m68000 processor core (mc68302, mc68306, mc68307, etc.) this fea- ture is not available, and a rom/ram swap technique is necessary to exchange the usual rom at address $0 with ram. this section demonstrates a ram/rom swap mechanism specifically for the mc68307. however, the method can be applied equally to the other m68000 core based members of the mc68300 family. 10.5.1 software implementation the swap mechanism relies on a section of position-independent code and careful repro- gramming of the chip selects registers during boot up. section 10.5.1.1 software listing 4 provides full details of the code used. initially, the rom and ram chip selects reserve areas in the memory map at base address $0 and address $200000 respectively. thereafter, a swap code routine is copied from rom into ram, before jumping to ram to execute it. on completion, the execution returns to con- tinue in rom, which is now relocated at base address $080000. finally, the ram is then relocated at base address $0 as required. the resulting memory map is shown in figure 10- 7.
applications information 10-28 mc68307 user? manual motorola figure 10-7. memory map after swap complete the method described uses an application with 512 kbytes of eprom and 128 kbytes of sram. if further details of the hardware are required, a full description is available in an490, titled ?ultiple bus interfaces using the mc68307? the swap relies on the code being loaded at address $080000 during the link process, although, any other multiple of the rom size could be used (e.g., $080000, $100000 and so on....), so long as the rom chip select is programmed accordingly. 10.5.1.1 software listing 4 * * 68307 processor registers. reg_base equ $fff000 ; start of internal registers mbar equ $0000f2 ; base address register scr equ $0000f4 ; system control register(32 bits) br0 equ reg_base+$040 ; cs0 base register or0 equ reg_base+$042 ; cs0 option register br1 equ reg_base+$044 ; cs1 base register or1 equ reg_base+$046 ; cs1 option register wrr equ reg_base+$12a ; software watchdog reference reg * tmp_base equ $00200000 ; temp ram base for rom/ram swap * * start-up code section sect 9,c dc.l stack ; initial sp dc.l $08 ; initial pc start and.w #$ffff,mbar ; 68307 register base at $fff000 move.w #$0000,wrr ; disable software watchdog move.w #$1f02,or0 ; 0 waits, 512kb block, r/w not masked, rom ram 000000 01ffff 080000 0fffff fff000 comments 16-bit wide 0 wait state address board feature 8 or 16 bit, programmable mc68307 registers range via mc68307 mbar 0 wait state
applications information motorola mc68307 user? manual 10-29 ; fc's masked move.w #$c001,br0 ; cs0 supervisor program space, base $0, ; read, en move.w #$1fc0,or1 ; 0 waits, 128kb block, r/w bit masked, ; fc's masked move.w #$a401,br1 ; cs1 supervisor data space, base ; $200000, read, en * * copy swap code to ram * lea swapc(pc),a0 ; get start address of swap code lea swapce(pc),a1 ; get end address of swap code movea.l #tmp_base,a2 ; get address of temp ram base swaplp cmpa.l a0,a1 ; has all code been copied? beq jumpsc ; if so, jump to code ram move.w (a0)+,(a2)+ ; otherwise, copy rom code to ram bra swaplp ; continue in swapping loop jumpsc jmp (tmp_base).l ; execute swap code in ram * * code for ram to $0 and rom to $80000 swap * a section of code is set up to relocate rom to $80000 * this is copied to ram, jumped to in ram and executed, * before jumping back to rom and relocating ram at $0. * swapc move.w #$c101,br0 ; place rom at $80000 by writing to br0 jmp (swapce).l ; return back to new rom location swapce move.w #$a001,br1 ; place ram at $0 by writing to br1
motorola mc68307 user? manual 11-1 section 11 electrical characteristics this section contains detailed information on power considerations, dc/ac electrical char- acteristics, and ac timing specifications of the mc68307. refer to section 12 ordering information and mechanical data for specific part numbers corresponding to voltage, fre- quency, and temperature ratings. 11.1 maximum ratings the following ratings define a range of conditions in which the device will operate without being damaged. however, sections of the device may not operate normally while being exposed to the electrical extremes. 11.2 thermal characteristics rating symbol value unit this device contains protective circuitry against damage due to high static voltag- es or electrical fields; however, it is ad- vised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of op- eration is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). supply voltage 1, 2 v cc ?.3 to + 7.0 v input voltage 1, 2 v in ?.3 to + 7.0 v operating temperature range t a ?0 to 85 c storage temperature range t stg ?5 to +150 c notes: 1.permanent damage can occur if maximum ratings are exceeded. exposure to voltages or currents in excess of recommended values affects device reliability. device modules may not operate normally while being exposed to electrical extremes. 2.although sections of the device contain circuitry to protectagainst damage from high static voltages or electrical ?lds, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. characteristic symbol value unit thermal resistance?unction to case plastic 100-pin qfp plastic 100-pin thin qfp q jc 20 1 20 1 c/w thermal resistance?unction to ambient plastic 100-pin qfp plastic 100-pin thin qfp q ja 42 1 42 1 c/w note: 1. estimated thi d t t d ith f m k 4 0 4
electrical characteristics 11-2 mc68307 user? manual motorola 11.3 power considerations the average chip-junction temperature, t j , in c can be obtained from: t j = t a + (p d ? q ja ) (1) where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d =p int + p i/o pint =i cc x v cc , watts?hip internal power p i/o = power dissipation on input and output pins?ser determined for most applications, p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d ?(t a + 273 c) + q ja ?p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at thermal equilibrium) for a known t a . using this value of k, the val- ues of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . 11.4 ac electrical specification definitions the ac specifications presented consist of output delays, input setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. the measurement of the ac specifications is defined by the waveforms shown in figure 11- 1. to test the parameters guaranteed by motorola, inputs must be driven to the voltage lev- els specified in that figure. outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in figure 11-1. inputs are specified with minimum setup and hold times and are measured as shown. finally, the measurement for signal-to- signal specifications is also shown. note the testing levels used to verify conformance to the ac specifi- cations do not affect the guaranteed dc operation of the device as specified in the dc electrical specifications.
electrical characteristics motorola mc68307 user? manual 11-3 figure 11-1. drive levels and test points for ac specifications 0.8 v 2.0 v b 2.0 v 0.8 v valid output n valid output n + 1 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v valid output n valid output n+1 2.0 v 0.8 v b a valid input 2.0 v 0.8 v 2.0 v 0.8 v d valid input 2.0 v 0.8 v 2.0 v 0.8 v d drive to 0.5 v drive to 2.4 v 2.0 v 0.8 v 2.0 v 0.8 v f clkout outputs(1) outputs(2) inputs(3) inputs(4) all signals(5) notes: 1. this output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. this output timing is applicable to all parameters specified relative to the falling edge of the clock. 3. this input timing is applicable to all parameters specified relative to the rising edge of the clock. 4. this input timing is applicable to all parameters specified relative to the falling edge of the clock. 5. this timing is applicable to all parameters specified relative to the assertion/negation of another signal. legend: a. maximum output delay specification. b. minimum output hold time. c. minimum input setup time specification. d. minimum input hold time specification. e. signal valid to signal valid specification (maximum or minimum). f. signal valid to signal invalid specification (maximum or minimum). e a c c
electrical characteristics 11-4 mc68307 user? manual motorola 11.5 dc electrical specifications 11.6 ac electrical specifications?lock timing (see figure 11-2) characteristic symbol min max unit input high voltage (except extal) v ih 2.0 v cc v input low voltage v il gnd ?0.3 0.8 v clock input high voltage (extal) vihc 0.7 v cc v cc + 0.3 v input leakage current @5.25v (all input-only pins) 1 i in ?2.5 2.5 m a three-state (off state) input current @2.4v/0.4v i tsi ?0 m a output high voltage (i oh = 4ma) v oh v cc ?0.75 ? output low voltage (i ol = 4ma) v ol 0.5 v current dissipation v cc = 5.0v 0.5v 2 , f ext = 16.67mhz v cc = 3.3v 0.3v 2 , f ext = 8mhz low power sleep mode v cc = 5.0v 0.5v, f ext = 16.67mhz v cc = 3.3v 0.3v, f ext = 8mhz i d tbd tbd tbd tbd ma power dissipation v cc = 5.0v 0.5v, f ext = 16.67mhz v cc = 3.3v 0.3v, f ext = 8mhz p d tbd tbd w input capacitance 3 all input-only pins all i/o pins c in 10 20 pf load capacitance 3 all output pins (except scl and sda) scl, sda c l 100 400 pf notes: 1. not including internal pull-up or pull-down. 2. currents listed are with no loading. 3. capacitance is periodically sampled rather than 100% tested. num characteristic 3.3 v 3.3 v or 5 v 8.33 mhz 16.67 mhz min max min max frequency of operation 0.0 8.33 0.0 16.67 1 clock period (extal) 120 60 2,3 clock pulse width (extal) 54 27 4,5 clock rise and fall times (extal) ??
electrical characteristics motorola mc68307 user? manual 11-5 11.7 ac electrical specifications?ead and write cycles (v cc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; t a = t l to t h ) (see figure 11-3 and figure 11-4 ) figure 11-2. clock timing num characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max 6 clock low to address valid 60 30 ns 7 clock high to address, data bus high impedance (maximum) 100 50 ns 8 clock high to address invalid (minimum) 0?ns 9 1 clock high to as , csx , lds , uds asserted 3 60 3 30 ns 11 2 address valid to as , csx , lds , uds asserted (read)/as , csx asserted (write) 30?5ns 12 1 clock low to as , csx , lds , uds negated 3 60 3 30 ns 13 2 as , csx , lds , uds negated to address invalid 30 15 ns 14 2 as , csx , (and lds , uds read) width asserted 240 120 ns 14a 2 lds , uds width asserted (write) 120 60 ns 15 2 as , csx , lds , uds width negated 120 60 ns 16 clock high to control bus high impedence 100 50 ns 17 2 as , csx , lds , uds negated to r/w invalid 30 15 ns 18 1 clock high to r/w high (read) 0 60 0 30 ns 20 1 clock high to r/w low (write) 0 60 0 30 ns 20a 2,3 as , csx , asserted to r/w low (write) 20 10 ns 21 2 address valid to r/w low (write) 0?ns 22 2 r/w low to lds , uds asserted (write) 60 30 ns 23 clock low to data-out valid (write) 60 30 ns 25 2 as , csx , lds , uds negated to data-out invalid (write) 30 15 ns 26 2 data-out valid to lds ,uds asserted (write) 30 15 ns 27 4 data-in valid to clock low (setup time on read) 10 5 ns 28 2 as , csx , lds , uds negated to dtack negated (asynchronous hold) 0 220 0 110 ns 29 as , csx , lds , uds negated to data-in invalid (hold time on read) 0?ns 29a as , csx , lds , uds negated to data-in high impedance 180 90 ns 31 2,4 dtack asserted to data-in valid (setup time) 100 50 ns 32 halt ,reset and rstin input transition time 0 300 0 150 ns 33 clock high to bg asserted 0 40 0 20 ns 0.8 v 3.8 v timing measurements are referenced to and from a low voltage of 0.8 v and a high voltage of 3.8 v, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 v and 3.8 v. note: 4 5 1 2 3
electrical characteristics 11-6 mc68307 user? manual motorola 34 clock high to bg negated 0 40 0 20 ns 35 9 br asserted to bg asserted (for last cycle of operand transfer) 1.5 3.5 1.5 3.5 clks 36 br negated to bg negated 1.5 3.5 1.5 3.5 clks 37 bgack asserted to bg asserted 1.5 3.5 1.5 3.5 clks 37a 2 bgack asserted to br negated 40 ns 1.5 20 ns 1.5 clks 38 bg asserted to control, address, data bus high impedance (as , csx negated) 100 50 ns 39 bg width negated 1.5 1.5 clks 46 bgack width low 1.5 1.5 clks 47 4 asynchronous input setup time 10 5 ns 53 data-out hold from clock high 0?ns 55 r/w asserted to data bus impedance change 0?ns 56 5 halt /reset pulse width, rstin pulse width 10 10 clks 57 bgack negated to as , csx , lds , uds , r/w driven 1.5 1.5 clks 58 br negated to as , csx , lds , uds , r/w driven 1.5 1.5 clks notes: 1. for a loading capacitance of less than or equal to 50 pf, subtract 5 ns from the value given in the maximum columns. 2. actual value depends on clock period. 3. when as , csx and r/w are equally loaded ( 20%), subtract 5 ns from the values given in these columns. 4. if the asynchronous input setup time (#47) requirement is satis?d for dt ack , the dt ack asserted to data setup time (#31) requirement can be ignored. the data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. 5. for power-up, the mc68307 is held in the reset state for 32768 clock cycles after v cc becomes stable to allow stabilization of on-chip circuitry. after the system is powered up, #56 refers to the minimum pulse width of reset / hal t required to reset the controller. this pulse is stretched internally to 132 clocks. if rstin is used, the pulse is stretched internally to 32768 clocks, and reset and hal t are asserted as outputs. 6. the processor will negate bg and begin driving the bus again if external arbitration logic negates br before asserting bgack . 7. the minimum value must be met to ensure proper operation. if the maximum value is exceeded, bg may be reeasserted. 8. as is always asserted, regardless of whether it is mapped to internal or external peripherals/memory. if the designer wishes to decode more chip selects than are provided, one of cs0 ?cs3 should be used as the enable for the external decode. 9. during a read modify write cycle or a dynamically sized cycle, bg is delayed if br is asserted before the last bus cycle of the operand transfer, in order to ensure operand coherency. bg will be asserted once as has asserted for the last bus cycle of the transfer. num characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max
electrical characteristics motorola mc68307 user? manual 11-7 figure 11-3. read cycle timing diagram 13 14 12 47 28 29 27 47 47 32 56 47 32 a23?0 csx, as lds / uds r/w dtack d15?0 br (note 2) halt / reset, 47 asynchronous inputs (note 1) 31 11a 2. br need fall at this time only to ensure being recognized at the end of the bus cycle. 8 9 15 6 11 29a notes: 1. setup time (#47) for asynchronous inputs (halt, reset, br, bgack, dtack, irq7, intx) guarantees their recognition at the next falling edge of the clock. 18 s0 s1 s2 s3 s4 s5 s6 clk s7 17 rstin
electrical characteristics 11-8 mc68307 user? manual motorola figure 11-4. write cycle timing diagram s0 s1 s2 s3 s4 s5 s6 clk s7 8 15 13 9 14 12 17 18 a23?0 csx, as lds / uds r/w 11 9 21 22 20 11a 14a 20a (note 2) (note 2) 6 47 28 25 26 48 47 47 32 56 47 32 dtack d15?0 br (note 3) halt / reset, 47 asynchronous inputs (note 1) 23 7 53 55 2. because of loading variations, r/w may be valid after as even though both are initiated by the rising edge of s2 (specification #20a). notes: 1. setup time (#47) for asynchronous inputs (halt, reset, br, bgack, dtack, irq7, intx) guarantees their recognition at the next falling edge of the clock. 3. br need fall at this time only to ensure being recognized at the end of the bus cycle. 15a rstin
electrical characteristics motorola mc68307 user? manual 11-9 11.8 ac electrical specifications?us arbitration (see figure 11-5 and figure 11-6.) num characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max 7 clock high to address, data bus high impedance (maximum) 100 50 ns 16 clock high to control bus high impedence 100 50 ns 33 clock high to bg asserted 0 40 0 20 ns 34 clock high to bg negated 0 40 0 20 ns 35 br asserted to bg asserted (for last cycle of operand transfer) 1.5 3.5 1.5 3.5 clks 36 br negated to bg negated 1.5 3.5 1.5 3.5 clks 37 bgack asserted to bg asserted 1.5 3.5 1.5 3.5 clks 37a 1 bgack asserted to br negated 40 ns 1.5 20 ns 1.5 clks 38 bg asserted to control, address, data bus high impedance (as , csx negated) 100 50 ns 39 bg width negated 1.5 1.5 clks 47 2 asynchronous input setup time 10 5 clks 57 bgack negated to as , csx , lds , uds , r/w driven 1.5 1.5 clks 58 br negated to as , csx , lds , uds , r/w driven 1.5 1.5 clks notes: 1. actual value depends on clock period. 2. if the asynchronous input setup time (#47) requirement is satis?d for dt ack , the dt ack asserted to data setup time (#31) requirement can be ignored. the data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. figure 11-5. three-wire bus arbitration diagram 37a 36 37 46 39 34 33 38 35 strobes and r/w br bgack bg clk note: setup time to the clock (#47) for the asynchronous inputs bgack , br , dtack , halt , reset , irq7 and intx guarantees their recognition at the next falling edge of the clock.
electrical characteristics 11-10 mc68307 user? manual motorola figure 11-6. two-wire bus arbitration timing diagram clk 33 35 br bg as u ds, lds r/w a19?0 d7?0 47 38 36 58 34 39 47 16 7 csx
electrical characteristics motorola mc68307 user? manual 11-11 11.9 ac electrical specifications?051 bus interface module (v cc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; t a = t l to t h ) (see figure 11-7 and figure 11-8.) refer to section 3 bus operation for a description of the 8051 diagram relative to the underlying 68000 bus cycle. symbol characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max t cyc cycle time 120 60 ns tlhll ale pulse width high t cyc ?30 t cyc ?15 ?s tavll address valid to ale low 1.5 x t cyc ?30 1.5 x t cyc ?15 ?s tllax address hold after ale low t cyc ?60 t cyc ?30 ?s trlrh rd pulse width asserted 1 4.5 x t cyc ?30 4.5 x t cyc - 15 ?s twlwh wr pulse width asserted 1 4.5 x t cyc ?30 4.5 x t cyc - 15 ?s trldv rd asserted to valid data in 1 4.5 x t cyc ?70 4.5 x t cyc ?35 ns trhdx data hold after rd negated 0 0 ns trhdz data float after rd negated 0.5 x t cyc 0.5 x t cyc ns tlldv ale low to valid data in 1 7.5 x t cyc ?70 7.5 x t cyc ?35 ns tavdv address to valid data in 1 9 x t cyc ?70 9 x t cyc ?35 ns tllwl ale low to rd or wr asserted 3 x t cyc ?57 3 x t cyc + 57 3 x t cyc ?27 3 x t cyc + 27 ns tavwl address valid to rd or wr asserted 4.5 x t cyc ?30 4.5 x t cyc ?15 ?s tqvwx data valid to wr asserted t cyc ?60 t cyc ?30 ?s tqvwh data valid to wr negated 1 5.5 x t cyc ?60 5.5 x t cyc ?30 ?s twhqx data hold after wr negated t cyc ?90 t cyc ?45 ?s trlaz rd asserted to address float 0 0 ns twhlh rd or wr negated to ale high 1.5 x t cyc ?30 1.5 x t cyc + 30 1.5 x t cyc ?15 1.5 x t cyc + 15 ns notes: 1. wait states can be added. 2. the values in the table are for the minimum 6 wait states of 8051 mode.
electrical characteristics 11-12 mc68307 user? manual motorola figure 11-7. external 8051 bus read cycle figure 11-8. external 8051 bus write cycle ale rd ad7?d0 a23?8 address data in address tlhll twhlh tlldv tllwl trlrh tavll tllax trldv trhdz trlaz trhdx tavwl tavdv ale wr ad7?d0 a23?8 address data out address tlhll twhlh tllwl twlwh tavll tllax twhqx tavwl tqvwx tqvwh
electrical characteristics motorola mc68307 user? manual 11-13 11.10 timer module electrical characteristics (v cc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; t a = t l to t h ) (see figure 11-9.) num characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max 1 tin clock low pulse width 1?clk 2 tin clock high pulse width and input capture high pulse width 2?clk 3 tin clock cycle time 3?clk 4 clock high to tout valid 70 35 ns figure 11-9. timer module timing diagram clkout t out (output) 4 32 1 tin (input) 1
electrical characteristics 11-14 mc68307 user? manual motorola 11.11 uart electrical characteristics (vcc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; ta = tl to th) (see figure 11-10 and figure 11-11.) num characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max 1 txd output valid from txc low 200 100 ns 2 rxd data setup time to rxc high 480 240 ns 3 rxd data hold time from rxc high 400 200 ns figure 11-10. transmitter timing figure 11-11. receiver timing clock 1 bit time txd (1 or 16 clocks) 1 clock 1x rxd 2 3
electrical characteristics motorola mc68307 user? manual 11-15 11.12 ac electrical characteristics?-bus input signal timing (v cc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; t a = t l to t h ) (see figure 11-12.) 11.13 ac electrical characteristics?-bus output signal timing (v cc = 5.0v 0.5v or 3.3vdc 0.3v; gnd = 0vdc; t a = t l to t h ) (see figure 11-12.) num characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max 1 start condition hold time 2?clk 2 clock low period 4.7 4.7 clk 3 sda/scl rise time ?? m s 4 data hold time 0?clk 5 sda/scl fall time 600 300 ns 6 clock high period 4?clk 7 data setup time 500 250 m s 8 start condition setup time (for repeated start condition only) 2?clk 9 stop condition setup time 2?clk num characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max 1 start condition hold time 8 8 clk 2 clock low period 11 11 clk 3 sda/scl rise time 2 1 m s 4 data hold time 0 2 0 2 clk 5 sda/scl fall time 600 300 ns 6 clock high period 11 11 clk 7 data setup time spec 2 x clk spec 2 x clk ?s 8 start condition setup time (for repeated start condition only) 20 10 clk 9 stop condition setup time 20 10 clk figure 11-12. m-bus interface input/output signal timing 5 sda scl 9 8 7 6 3 2 4 1
electrical characteristics 11-16 mc68307 user? manual motorola 11.14 ac electrical characteristics?ort timing (see figure 11-13.) characteristic symbol 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max port input setup time to uds , lds asserted t ps 0?ns port input hold time from uds , lds negated t ph 0?ns port output valid from uds , lds negated t pd ?0?0ns note: test conditions for port outputs: c l = 50 pf, r l = 27 k w to v cc . figure 11-13. port timing t ps uds, lds p orta, portb p orta, portb old data new data t pd t ph
electrical characteristics motorola mc68307 user? manual 11-17 11.15 ieee 1149.1 electrical characteristics (see figure 11-14, figure 11-15, and figure 11-16.) num. characteristic 3.3v 3.3 v or 5 v unit 8.33 mhz 16.67 mhz min max min max tck frequency of operation 0 10.0 0 5.0 mhz 1 tck cycle time 100 200 ns 2 tck clock pulse width measured at 1.5 v 45 45 ns 3 tck rise and fall times 0 5 0 10 ns 6 boundary scan input data setup time 15 30 ns 7 boundary scan input data hold time 15 30 ns 8 tck low to output data valid 0 80 0 160 ns 9 tck low to output high impedance 0 80 0 160 ns 10 tms, tdi data setup time 15 30 ns 11 tms, tdi data hold time 15 30 ns 12 tck low to tdo data valid 0 30 0 60 ns 13 tck low to tdo high impedance 0 30 0 60 ns figure 11-14. test clock input timing diagram v v tck 1 2 2 3 3 ih il
electrical characteristics 11-18 mc68307 user? manual motorola figure 11-15. boundary scan timing diagram figure 11-16. test access port timing diagram tck data outputs data inputs data outputs data outputs v v input data valid output data valid output data valid 7 8 il ih 6 9 8 tclk tdi tms tdo tdo tdo v v input data valid output data valid output data valid 11 12 13 12 il ih 10
motorola mc68307 user? manual 12-1 section 12 ordering information and mechanical data this section contains the ordering information, pin assignments, and package dimensions for the mc68307. 12.1 standard ordering information package type frequency (mhz) supply voltage (v) temperature order number 100-pin plastic quad flat pack (fg suffix) 16.67 5 0 c to 70 c MC68307FG16 100-pin thin quad flat pack (pu suffix) 16.67 5 ?0 c to 70 c mc68307pu16 100-pin plastic quad flat pack (fg suffix) 16.67 5 ?0 c to 85 c mc68307cfg16 100-pin plastic quad flat pack (fg suffix) 16.67 3.3 ?0 c to 70 c MC68307FG16v 100-pin thin quad flat pack (pu suffix) 8.33 3.3 ?0 c to 70 c mc68307pu8v 100-pin thin quad flat pack (pu suffix) 16.67 3.3 ?0 c to 70 c mc68307pu16v thi d t t d ith f m k 4 0 4
ordering information and mechanical data 12-2 mc68307 user? manual motorola 12.2 100-pin pqfp pin assignments (fg suffix) a13 a12 a11 a10 gnd a9 a8 a7/ad7 a6/ad6 a5/ad5 a22 a21 a20 a19 a18 vcc a17 a16 a15 a14 d7 d6 d5 d4 vcc d3 d2 d1 d0 tdo tms d15 d14 d13 d12 gnd d11 d10 d9 d8 79 52 80 81 100 1 30 31 50 51 pb0/scl pb1/sda vcc pb2/txd pb3/rxd pb4/r ts pb5/cts pb6/tin1 pb7/tin2 pb8/int1 pb10/int3 pb11/int4 pb12/int5 pb13/int6 pb14/int7 pb15/int8 vcc pa0/cs2b pa1/cs2c pa2/cs2d pa3/tout1 pa4/tout2 pa5/br pa6/bg gnd pa7/bga ck irq7 a23 pb9/int2 gnd rstin vcc hal t reset tck cs0 cs1 cs2a /cs2 cs3 gnd tdi ale rd gnd wr as uds lds r/w dt a ck clkout extal xtal busw a0/ad0 a1/ad1 a2/ad2 vcc a3/ad3 a4/ad4 mc68307 (top view)
ordering information and mechanical data motorola mc68307 user? manual 12-3 12.3 100-pin pqfp package dimensions (fg suffix) dim. min. max. notes dim. min. max. a 19.90 20.10 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. all dimensions in mm. 3. datum plane ??is located at the bottom of the lead and is coincident with the lead where it exits the plastic body at the bottom of the parting line. 4. datums a? and ??to be determined at datum plane ?? 5. dimensions s and v to be determined at seating plane ?? 6. dimensions a and b do not include mould protrusion; allowable protrusion is 0.25mm per side. dimensions a and b do include mould mismatch and are determined at datum plane ?? 7. dimension d does not include dambar protrusion; allowable protrusion is 0.08mm total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. p 0.325 bsc b 13.90 14.10 q 0 7 c 2.85 3.15 r 0.13 0.30 d 0.22 0.38 s 23.10 23.37 e 2.55 3.05 t 0.13 f 0.22 0.33 u 0 g 0.65 bsc v 17.10 17.37 h 0.25 0.35 w 0.40 j 0.13 0.23 x 1.60 ref k 0.75 0.92 y 0.58 ref l 12.35 ref z 0.83 ref m5 16 aa 18.85 ref n 0.13 0.17 ? l v 0.2 c a? d ms s 0.2 h a? d ms s z aa y ? ? a 0.05 a? s 0.2 h a? d ms s b 0.2 c a? d ms s 0.05 a? case no. 842b-01 qfp-100 14x20 130 51 80 31 50 81 100 p ?, b, d detail ? detail ? j f n d 0.2 c a? d ms s base metal detail ? ? seating plane h e c g detail ? 0.10 ? datum plane detail ? m m detail ? ? datum plane x k q r u w t
ordering information and mechanical data 12-4 mc68307 user? manual motorola 12.4 100-pin tqfp pin assignments (pu suffix) vdd d5 d4 d3 26 27 29 30 31 32 33 34 35 36 38 39 40 41 28 75 74 72 71 70 69 68 67 66 65 64 63 62 61 60 73 vdd pb2/txd pb4/rts pb5/cts pb6/tin1 pb7/tin2 pb8/int1 pb9/int2 pb10/int3 vss pb11/int4 pb12/int5 pb13/int6 pb14/int7 pb15/int8 pb3/rxd vss wr uds lds r/w dtack rstin vdd halt reset tck cs0 cs1 cs2a /cs2 cs3 as a3/ad3 a4/ad4 a6/ad6 a7/ad7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a5/ad5 rd ale tdo d0 d1 d2 d6 d7 d8 d9 d10 tdi 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 3 vss 37 100 99 97 96 95 94 92 91 90 89 88 87 86 85 98 93 59 58 57 56 55 54 53 52 51 vdd pa0/cs2b pa1/cs2c pa2/cs2d pa3/tout1 pa4/tout2 pa5/br pa6/bg vss vss d13 d12 d11 d14 d15 tms pb0/scl pb1/sda 83 82 81 80 79 78 77 76 84 18 20 19 17 21 22 23 24 25 clkout extal xtal busw a0/ad0 a1/ad1 a2/ad2 vdd vss 43 45 44 42 46 47 48 49 50 a18 a19 a20 a21 a22 a23 irq7 pa7/bgack vdd mc68307 (top view)
ordering information and mechanical data 12-5 mc68307 user? manual motorola 12.5 100-pin tqfp package dimensions (pu suffix) !($
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motorola mc68307 user? manual index-1 index numerics 8051-compatible bus 2-9, 5-8 8051-compatible bus interface 5-10 a a23?0 2-5 access errors 4-1 ad7?d0 2-6 address bus 2-5 address latch enable 2-9 address strobe 2-8 addressing modes 4-4 index sizing and scaling 4-3 indexing 4-3 offset 4-3 postincrement 4-3 predecrement 4-3 program counter indirect 4-3 register indirect 4-3 ale 2-9 as 2-8, 3-4, 3-7, 3-8, 3-18 asynchronous bus arbitration signals 3-19 asynchronous mode 3-32 b base registers 5-30 baud rate generator 8-5 berr 3-4 bg 2-10, 3-18 bgack 2-10 boundary scan 9-1 boundary scan bit definitions 9-4 br 2-10 br3-br0 5-30 bus arbitration 3-15 2-wire 3-15 3-wire 3-15 bus control signals 2-7 bus error exception 3-31 bus grant 2-10 bus grant acknowledge 2-10 bus grant signal 3-16 bus request 2-10 bus width select 2-9 busw0 2-9 byte read cycle flowchart 3-2 c chip select registers 5-30 chip selects 1-5, 2-6, 5-5 clear-to-send 2-12 clkout 2-11 clock output 2-11 clock signals 2-10 crystal oscillator 2-10 cs0 2-6 cs1 2-6 cs2 2-6 cs3 2-7 cts 2-12 d data bus 2-6, 3-29 data formats 4-3 data strobes 2-8 data transfer acknowledge 2-7 data types denormalized numbers 4-3 infinities 4-3 nans 4-3 normalized numbers 4-3 zeros 4-3 denormalized numbers 4-3 double bus fault 3-31 dtack 2-7, 3-4 dual timer module 6-1 thi d t t d ith f m k 4 0 4
index index-2 mc68307 user? manual motorola e ebi 1-5 eprom memory interface 10-5 eprom timing 10-6 exceptions 4-9 access errors 4-1 address error exception 4-18 bus error exception 4-18 control signals 2-9 exception vector 4-12 exceptions handler 4-10 reset exception 4-14 sr m-bit 4-10 trace exception 4-17 vector assignments 4-13 vector table 4-9 extal 2-10 external bus interface 1-5 control registers 5-34 logic 5-9 f fifo stack 8-8 floating-point unit (see data types) function codes 3-29 g general purpose timer units 6-4 general-purpose i/o ports 5-10 general-purpose interrupt inputs 5-17 general-purpose timer units 6-1 global chip select operation 5-8 h halt 2-10 halt 2-10 i i/o driver routines 8-31 index sizing and scaling 4-3 indexing 4-3 infinities 4-3 initialization routines 8-31 instructions stop 4-1 trap, trapv, chk, rte, and div 4-9 int1 - int8 2-13 interrupts 4-1 acknowledge bus cycle 4-9 control registers 5-38 controller logic 5-14 general-purpose interrupt inputs 5-17 handling routine 8-31 latched interrupt control registers 5-38 level 7 interrupts 4-14 non-maskable interrupt 5-17 peripheral interrupt control register 5-39 peripheral interrupt handling 5-18 priorities 4-14 priority mask 4-9 processing 5-13 requests 4-15 inputs 2-13 signals 8-3 uninitialized interrupt vector 4-15 vector generation 5-15 irq7 2-13, 5-17 j jtag 9-1 instruction register 9-9 l latched interrupt control registers 5-38 lds 2-8, 3-7 licr1, licr2 5-38 looping modes 8-10 low-power sleep mode 10-9 low-power stop logic 5-19 low-power stop mode 10-9 m m68000 bus interface 5-9 mbar 5-22 m-bus address register 7-6 arbitration lost 7-13 arbitration procedure 7-4 clock stretching 7-5
index motorola mc68307 user? manual index-3 clock synchronization 7-4 control register 7-7 data i/o register 7-10 data transfer 7-3 frequency divider register 7-6 generation of repeated start 7-13 generation of start 7-11 generation of stop 7-12 handshaking 7-5 i/o signals 2-11 initialization sequence 7-10 interface module 7-1 interrupt routine 7-14 master mode 10-12 module 1-6 post-transfer software 7-11 programming examples 7-10 programming model 7-5 protocol 7-2 registers madr 7-6 mbcr 7-7 mbdr 7-10 mbsr 7-9 mfdr 7-6 repeated start signal 7-4 slave address transmission 7-3 slave mode 7-13, 10-12 software 10-10 start signal 7-3 status register 7-9 stop signal 7-4 system configuration 7-2 module base address register 5-2, 5-22 n nans 4-3 non-ieee 1149.1 operation 9-11 non-maskable interrupt 5-17 non-maskable interrupt input 2-13 normalized numbers 4-3 o offset 4-3 operand size 4-3 option registers 5-32 or3-or0 5-32 overlap in chip-select ranges 5-8 p package dimensions pqfp 12-2 tqfp 12-4 pacnt 5-34 padat 5-35 paddr 5-35 parallel i/o ports 1-5 pb7 2-13 pbcnt 5-36 pbdat 5-37 pbddr 5-36 peripheral chip-selects 5-7 peripheral interrupt control register 5-39 peripheral interrupt handling 5-18 picr 5-39 pin assignments pqfp 12-1 tqfp 12-3 port a 5-10, 5-12 control register 5-34 data direction register 5-35 data register 5-35 port b 2-11?-13, 5-10, 5-12 control register 5-36 data direction register 5-36 data register 5-37 postincrement 4-3 power-on reset 2-10 predecrement 4-3 privileged instructions 4-17 processing states normal, exception, halted 4-1 program counter indirect 4-3 programmable data-bus size 5-6 r r/w 2-8, 3-4, 3-7 ram memory interface 10-5 ram timing 10-6 rd 2-9 read cycle 3-2 read/write 2-8
index index-4 mc68307 user? manual motorola read-modify-write cycle 3-8, 3-29 receive data 2-12 register indirect 4-3 request-to-send 2-12 reset 2-9 reset 2-9 rs232 uart port 10-5 rstin 2-10 rts 2-12 rxd 2-12 s scl 2-11 scr 5-23 sda 2-12 serial clock 2-11 serial data 2-12 serial module registers uacr 8-26 ubg1 8-29 ubg2 8-29 ucr 8-23 ucsr 8-21 uimr 8-28 uip 8-29 uipcr 8-26 uisr 8-27 uivr 8-29 urb 8-25 usr 8-19 utb 8-25 signal configuration 10-1 signal index 2-14 sim configuration 5-41 sim programming model 5-20 sim07 1-4 single-step 3-30 software listings 10-17?0-29 software watchdog timer 6-3, 6-7 stack frame 4-9 stand alone hardware 10-1 startup - cold reset 5-41 status register 4-9 swapping rom and ram mapping 10-27 system configuration and protection 1-5 registers 5-22 system control register 5-4, 5-23 system integration module 1-4, 5-1 system protection functions 5-5 t tap 9-1 tas 3-8 tck 2-11 tcn1, tcn2 6-5 tcr1, tcr2 6-5 tdi 2-11 tdo 2-11 ter1, ter2 6-6 test access port 1-7 test clock 2-11 test data in 2-11 test data out 2-11 test mode select 2-11 test signals 2-11 timer 1-6 capture registers 6-5 counter 6-5 event registers 6-6 i/o signals 2-12 mode register 6-4 reference registers 6-5 registers tcn1, tcn2 6-5 tcr1, tcr2 6-5 ter1, ter2 6-6 tmr1, tmr2 6-4 trr1, trr2 6-5 timer 1 input 2-12 timer 1 output 2-13 timer 2 input 2-13 timer 2 output 2-13 timer/counter 8-3 tin1 2-12 tin2 2-13 tmr1, tmr2 6-4 tms 2-11 tout1 2-13 tout2 2-13 transmit data 2-12 trr1, trr2 6-5 txd 2-12
index motorola mc68307 user? manual index-5 u uacr 8-26 uart driver examples 10-24 uart i/o signals 2-12 uart module 1-6 ubg1 8-29 ubg2 8-29 ucr 8-23 ucsr 8-21 uds 2-8, 3-7 uds /lds 3-4, 3-10 uimr 8-28 uip 8-29 uipcr 8-26 uisr 8-27 uivr 8-29 urb 8-25 usr 8-19 utb 8-25 v valid start bit 8-8 vector number 4-9 w wait state generation 1-5 wait-state logic 5-5 wake-up 10-8 watchdog counter register 6-7 watchdog reference register 6-7 wcr 6-7 word read cycle flowchart 3-2 wr 2-9 write cycle 3-5 wrr 6-7 x xtal 2-10 z zeros 4-3

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